MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 39

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.5 I/O Section
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Addresses $0000–$005F, shown in
control, status, and data registers. Additional I/O registers have these
addresses:
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$FE00, system integration module (SIM) break status register
(SBSR)
$FE01, SIM reset status register (SRSR)
$FE03, SIM break flag control register (SBFCR)
$FE08, FLASH control register (FLCR)
$FF57, FLASH test control register (FLTCR)
$FE0C, break address register high (BRKH)
$FE0D, break flag control register low (BRKL)
$FE0E, break status and control register (BRKSCR)
$FE0F, low-voltage inhibit (LVI) status and control register
(LVISCR)
$FF7E, FLASH block protect register (FLBPR)
$FFFF, computer operating properly (COP) control register
(COPCTL)
Memory Map
Figure
2-2, contain most of the
Technical Data
Memory Map
I/O Section
39