MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 43

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
U = Unaffected
nate
$001E
$001F
$0014
$0015
$0016
$0017
$0018
$0019
$0020
$0021
Addr.
↓
PWM Control Register 1
PWM Control Register 2
TIMA Channel 0 Regis-
TIMA Channel 0 Regis-
TIMA Channel 1 Regis-
TIMA Channel 1 Regis-
Configuration Register
TIMA Channel 1 Sta-
ter High (TACH0H)
ter High (TACH1H)
ter Low (TACH0L)
ter Low (TACH1L)
Register (TASC1)
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 10)
See page 222.
See page 218.
See page 222.
See page 222.
See page 222.
See page 175.
See page 177.
X = Indetermi-
See page 68.
tus/Control
(CONFIG)
(PCTL1)
(PCTL2)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read: CH1F
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
LDFQ1 LDFQ0
EDGE
Bit 15
Bit 15
DISX
Bit 7
Bit 7
Bit 7
R
0
0
0
0
0
= Reserved
CH1IE
BOT-
DISY
NEG
Memory Map
14
14
6
6
0
6
0
0
0
MINT
TOP-
NEG
PW-
13
13
R
5
5
0
0
5
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
SEL12
INDEP
PWMF
MS1A
Bold
Unimplemented
Unimplemented
12
12
4
4
0
4
0
0
0
ered
= Buff-
LVIRST
SEL34
ELS1B
11
11
3
3
0
3
1
0
0
LVIPWR STOPE
SEL56 PRSC1 PRSC0
ELS1A
10
10
2
2
0
2
1
0
0
= Unimplemented
LDOK
TOV1
Technical Data
1
9
1
0
9
1
0
0
0
Memory Map
I/O Section
CH1MA
COPD
MEN
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PW-
X
0
0
0
0
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