MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 48

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map
Technical Data
48
U = Unaffected
nate
$005C
$005D
$005A
$005B
$005E
$0055
$0056
$0057
$0058
$0059
Addr.
Register Low (TBMODL)
PLL Programming Reg-
TIMB Channel 0 Regis-
TIMB Channel 0 Regis-
TIMB Channel 1 Regis-
TIMB Channel 1 Regis-
PLL Bandwidth Control
TIMB Counter Modulo
TIMB Channel 0 Sta-
TIMB Channel 1 Sta-
PLL Control Register
tus/Control Register
tus/Control Register
ter High (TBCH1H)
ter High (TBCH0H)
ter Low (TBCH0L)
ter Low (TBCH1L)
Register (PBWC)
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 10)
See page 241.
See page 242.
See page 246.
See page 246.
See page 242.
See page 246.
See page 246.
See page 126.
See page 129.
See page 131.
X = Indetermi-
(TBSC0)
(TBSC1)
(PCTL)
(PPG)
ister
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read: CH0F
Read:
Read:
Read: CH1F
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
AUTO
PLLIE
MUL7
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
1
0
0
0
0
0
0
0
R
= Reserved
CH0IE
CH1IE
LOCK
MUL6
Bit 14
Bit 14
PLLF
Bit 6
Bit 6
Bit 6
Memory Map
R
R
6
1
0
0
0
0
1
PLLON
MS0B
MUL5
Bit 13
Bit 13
ACQ
Bit 5
Bit 5
Bit 5
R
5
1
0
0
0
1
0
1
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
MUL4
Bit 12
Bit 12
Bold
BCS
Bit 4
Bit 4
Bit 4
XLD
4
1
0
0
0
0
0
ered
= Buff-
ELS0B
ELS1B
VRS7
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
R
R
3
1
0
0
1
1
0
0
0
MC68HC908MR8 — Rev 4.1
ELS0A
ELS1A
Bit 10
Bit 10
VRS6
Freescale Semiconductor
Bit 2
Bit 2
Bit 2
R
R
1
0
0
1
1
0
0
1
2
= Unimplemented
TOV0
TOV1
VRS5
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
R
R
0
1
1
1
0
1
0
0
1
CH0MA
CH1MA
VRS4
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
R
R
X
X
1
0
0
1
1
0
0
0