MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 176

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Pulse-Width Modulator for Motor Control
Technical Data
176
CAUTION:
NOTE:
NOTE:
NOTE:
When PWMINT is cleared, pending CPU interrupts are inhibited.
PWMF— PWM Reload Flag
When PWMF is cleared, pending PWM CPU interrupts are cleared
(excluding fault interrupts).
Bits 2 and/or 3 of PCTL1 are reserved and must never be set to a 1.
Setting these bits to a 1 will affect the active PWM value registers.
Undesirable results will occur.
LDOK— Load OK Bit
The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
PWMEN — PWM Module Enable Bit
Pulse-Width Modulator for Motor Control (PWMMC)
This read/write bit is set at the beginning of every reload cycle
regardless of the state of the LDOK bit. This bit is cleared by reading
PWM control register 1 with the PWMF flag set, then writing a logic 0
to PWMF. If another reload occurs before the clearing sequence is
complete, then writing logic 0 to PWMF has no effect.
This read/write bit allows the counter modulus, counter prescaler, and
PWM values in the buffered registers to be used by the PWM
generator. These values will not be used until the LDOK bit is set and
a new PWM load cycle begins. LDOK may be cleared, if it is set, by
writing a logic 0 to it prior to the beginning of a new PWM load cycle.
Internally this bit is automatically cleared after the new values are
loaded.
This read/write bit enables and disables the PWM generator and the
PWM pins. When PWMEN is clear, the PWM generator is disabled
and the PWM pins are in the high-impedance state (unless
OUTCTL = 1). When the PWMEN bit is set, the PWM generator and
PWM pins are activated. For more information, see
and the PWMEN
1 = New reload cycle began.
0 = New reload cycle has not begun.
1 = Okay to load new modulus, prescaler, and PWM values at
0 = Not okay to load new modulus, prescaler, and PWM values
1 = PWM generator and PWM pins enabled
0 = PWM generator and PWM pins disabled
beginning of next PWM load cycle
Bit.
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
9.8 Initialization