ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 98

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

On-chip peripherals
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Register description
Timer control status register (ATCSR)
Reset value: 0x00 0000 (x0h)
Bit 7 = Reserved
Bit 6 = ICF Input Capture flag
Bit 5 = ICIE IC Interrupt Enable bit
Bits 4:3 = CK[1:0] Counter Clock Selection bits
Table 37.
Bit 2 = OVF1 Overflow flag
Bit 1 = OVFIE1 Overflow Interrupt Enable bit
This Bit is set by hardware and cleared by software by reading the ATICR register (a
read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change
the bit value.
0: No input capture
1: An input capture has occurred
This bit is set and cleared by software.
0: Input Capture Interrupt Disabled
1: Input Capture Interrupt Enabled
These bits are set and cleared by software and cleared by hardware after a reset. they
select the clock frequency of the counter.
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.
0: No Counter Overflow Occurred
1: Counter Overflow Occurred
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
7
0
Counter clock selection
ICF
f
LTIMER
Counter clock selection
selection forbidden
(1 ms timebase @ 8 MHz)
ICIE
OFF
f
CPU
CK1
Read / Write
CK0
ST7FOXF1, ST7FOXK1, ST7FOXK2
OVF1
OVFIE1
CK1
1
0
0
1
CMPIE
CK0
0
1
1
0
0