ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 159
![IC MCU 8BIT 1V FLASH MEM 32LQFP](/photos/12/33/123302/st7foxk1t6_sml.jpg)
ST7FOXK1T6
Manufacturer Part Number
ST7FOXK1T6
Description
IC MCU 8BIT 1V FLASH MEM 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FOXF1M6.pdf
(226 pages)
Specifications of ST7FOXK1T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FOXx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 1 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-6336
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FOXK1T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST7FOXK1T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 73. Serial peripheral interface block diagram
10.6.4
MOSI
MISO
SCK
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
but master and slave must be programmed with the same timing mode.
SOD
bit
SPIDR
Figure
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
74.
GENERATOR
CONTROL
MASTER
Data/Address Bus
Read
Write
7
SPIE
SPIF WCOL
7
SPE
CONTROL
SPR2
OVR
STATE
SPI
MODF
MSTR
Interrupt
Figure 77 on page
request
CPOL
0
On-chip peripherals
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
159/226
SSI
0
164)
0
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