ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 89

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

ST7FOXF1, ST7FOXK1, ST7FOXK2
Note:
2
1
Figure 42. ST7FOXK2 Block diagram of break function
Output compare mode
To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is
generated if the CMPIE bit is set.
In Single Timer mode the output compare function is performed only on CNTR1. The
difference between both the modes is that, in Single Timer mode, CNTR1 can be compared
with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0
or DCR1 and CNTR2 is compared with DCR2 or DCR3.
The output compare function is only available for DCRx values other than 0 (reset value).
Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers
and these values are transferred in Active Duty Cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these
active DCRx values with the counters.
Comparator2
BREAK2 pin
BREAKCR2 register
BR2SEL BR2EDGE
Comparator1
BREAK1 pin
BA2
BR1SEL
BP2EN
Level
Selection
BR1EDGE
Level
Selection
0
1
-
0
1
-
BA1
SWBR2
BP1EN
BREN1 bit
BREN2 bit
SWBR1
PWM3
BREAKCR1 register
ENCNTR2 bit
PWM2
PWM0/1 Break Enable
PWM2
PWM3
PWM0
PWM1
PWM1
PWM2/3 Break Enable
PWM0
(Inverters)
On-chip peripherals
OEx
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PWM0
PWM1
PWM2
PWM3