ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 116

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

On-chip peripherals
Table 41.
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Address
(Hex.)
0C
0D
0E
0F
10
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Bit 5 = TB Timebase period selection bit
Bit 4 = TB1IE Timebase Interrupt enable bit
Bit 3 = TB1F Timebase Interrupt flag
Bits 2:0 = Reserved, must be kept cleared.
Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
Bits 7:0 = ICR[7:0] Input Capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Lite Timer register mapping and reset values
Register
LTCNTR
LTCSR2
LTCSR1
LTARR
LTICR
label
ICR7
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
7
CNT7
ICR7
AR7
ICIE
ICR6
7
0
0
0
0
0
CNT6
ICR6
AR6
ICF
6
0
0
0
0
x
ICR5
OSC
OSC
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
CNT5
ICR5
AR5
TB
5
0
0
0
0
0
ICR4
Read only
TB1IE
CNT4
ICR4
AR4
4
0
0
0
0
0
ICR3
CNT3
TB1F
ST7FOXF1, ST7FOXK1, ST7FOXK2
ICR3
AR3
3
0
0
0
0
0
ICR2
CNT2
ICR2
AR2
2
0
0
0
0
0
ICR1
TB2IE
CNT1
ICR1
AR1
1
0
0
0
0
0
ICR0
CNT0
TB2F
ICR0
AR0
0
0
0
0
0
0
0