ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 40

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

Supply, reset and clock management
6.3
6.3.1
Note:
Caution:
40/226
Table 8.
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte.
The Reset vector fetch phase duration is 2 clock cycles.
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (see
Section 11.2.1 on page 184
ST7 clock sources
for further details.
Hardware configuration
C
L1
OSC1
OSC1
CAPACITORS
Table
LOAD
ST7
ST7
13)
OSC2
OSC2
ST7FOXF1, ST7FOXK1, ST7FOXK2
C
L2
Figure
13:
Figure
14: