ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 151

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 1 = STOP Generation of a Stop condition bit
Bit 0 = ITE Interrupt Enable bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure
71) is detected.
Figure 72
for the relationship between the events and the interrupt.
On-chip peripherals
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