ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 84

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

On-chip peripherals
10.2.3
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Functional description
PWM mode
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins.
PWM frequency
The four PWM signals can have the same frequency (f
frequencies. This is selected by the ENCNTR2 bit which enables Single Timer or Dual
Timer mode (see
period and the ATR register value. In Dual Timer mode, PWM2 and PWM3 can be
generated with a different frequency controlled by CNTR2 and ATR2.
Following the above formula, if f
2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register
value = 0).
The maximum value of ATR is 4094 because it must be lower than the DC4R value
which must be 4095 in this case.
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload
registers. The DCRx values are transferred in Active duty cycle registers after an
overflow event if the corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit
controls the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx
values with the counter.
The maximum available resolution for the PWMx duty cycle is:
where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can
be obtained by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are
transferred to the active Duty Cycle registers and the PWMx signals are set to a high
level. When the upcounter matches the active DCRx value the PWMx signals are set to
a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active
DCRx register must be greater than the contents of the ATR register.
The maximum value of ATR is 4094 because it must be lower than the DCR value
which must be 4095 in this case.
Polarity inversion
The polarity bits can be used to invert any of the four output signals. The inversion is
synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See
Figure 35
f
PWM
Resolution
and
=
COUNTER
Figure
Figure
f
COUNTER
=
36). The frequency is controlled by the counter
37.
1
equals 4 MHz
⁄
(
⁄
4096 ATR
(
4096 ATR
–
ST7FOXF1, ST7FOXK1, ST7FOXK2
–
PWM
)
,
)
the maximum value of f
) or can have two different
PWM
is