ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 153

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 3 = BTF Byte Transfer Finished bit
Bit 2 = ADSL Address matched bit (slave mode). This bit is set by hardware as soon as the
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register
or by hardware when the interface is disabled (PE=0).
Bit 1 = M/SL Master/Slave bit
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
–
–
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See
next byte in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
Figure
71). BTF is cleared by reading SR1 register followed by writing the
On-chip peripherals
153/226