ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 106
![IC MCU 8BIT 1V FLASH MEM 32LQFP](/photos/12/33/123302/st7foxk1t6_sml.jpg)
ST7FOXK1T6
Manufacturer Part Number
ST7FOXK1T6
Description
IC MCU 8BIT 1V FLASH MEM 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FOXF1M6.pdf
(226 pages)
Specifications of ST7FOXK1T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FOXx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 1 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-6336
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FOXK1T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST7FOXK1T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
On-chip peripherals
Note:
Note:
Note:
106/226
Timer Control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
Bit 7 = FORCE2 Force Counter 2 Overflow bit
This bit must not be reset by software
Bit 6 = FORCE1 Force Counter 1 Overflow bit
This bit must not be reset by software
Bit 5 = ICS Input Capture Shorted bit
Bit 4 = OVFIE2 Overflow interrupt 2 enable bit
Bit 3 = OVF2 Overflow flag
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
FORCE2
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is
reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset
by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for
long Input Capture.
0 : ATIC for CNTR1 Input Capture
1 : LTIC for CNTR1 Input Capture
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It
indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2
counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
7
FORCE1
ICS
OVFIE2
Read/write
OVF2
ST7FOXF1, ST7FOXK1, ST7FOXK2
ENCNTR2
TRAN2
TRAN1
0