ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 105

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

ST7FOXF1, ST7FOXK1, ST7FOXK2
Input Capture register Low (ATICRL)
Reset value: 0000 0000 (00h)
Bits 11:0 = ICR[11:0] Input Capture Data.
Break Enable register (BREAKEN)
Reset value: 0000 0011 (03h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = BREN2 Break Enable for Counter 2 bit
Bit 0 = BREN1 Break Enable for Counter 1 bit
ICR7
This is a 12-bit register which is readable by software and cleared by hardware after a
reset. The ATICR register contains captured the value of the 12-bit CNTR1 register
when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS).
Capture will only be performed when the ICF flag is cleared.
This bit is read/write by software. It enables the break functionality for Counter2 if BA bit
is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
This bit is read/write by software. It enables the break functionality for Counter1. If BA
bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is
reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
7
7
0
ICR6
0
ICR5
0
ICR4
0
Read/write
Read only
ICR3
0
ICR2
0
On-chip peripherals
BREN2
ICR1
BREN1
ICR0
105/226
0
0