PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 50

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
5.5
PIC18F2331/2431/4331/4431
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.5.1
The Power-up Timer (PWRT) of PIC18F2331/2431/
4331/4431 devices is an 11-bit counter that uses the
INTRC source as the clock input. This yields an
approximate time interval of 2,048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset. The power-up time delay depends on the
INTRC clock and will vary from chip to chip due to tem-
perature and process variation. See DC Parameter 33
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
5.5.2
The Oscillator Start-up Timer (OST) provides a
1,024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes, and on Power-on Reset or on exit from
most power-managed modes.
TABLE 5-1:
DS39616D-page 50
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1:
Configuration
2:
Oscillator
Device Reset Timers
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the 4x PLL to lock.
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
TIME-OUT IN VARIOUS SITUATIONS
66 ms
66 ms
(1)
devices
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
incorporate
Power-up
OSC
(1)
(1)
(1)
+ 2 ms
OSC
(2)
(2)
and Brown-out
5.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
Lock Time-out (T
oscillator start-up time-out.
5.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT.
Figure 5-7
with the Power-up Timer enabled and the device oper-
ating in HS Oscillator mode.
Figure 5-6
modes.
For devices in RC mode, and with the PWRT disabled,
there will be no time-out at all. Since the time-outs
occur from the POR pulse, if MCLR is kept low long
enough, all time-outs will expire. Bringing MCLR high
will begin execution immediately
useful for testing purposes or synchronization of more
than one PIC18FXXXX device operating in parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, the PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
OSC
—
—
—
also apply to devices operating in XT or LP
depict time-out sequences on power-up,
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
OSC
PLL
(2)
) is typically 2 ms and follows the
 2010 Microchip Technology Inc.
Power-Managed Mode
1024 T
(Figure
Figure 5-3
1024 T
Exit From
Figure 5-3
OSC
—
—
—
5-5). This is
+ 2 ms
OSC
through
through
(2)