PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 305

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
=
=
=
=

=
register ‘f’
operation
operation
operation
Increment f, Skip if 0
[ label ]
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest,
skip if result = 0
None
The contents of register, ‘f’, are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register, ‘f’.
If the result is ‘0’, the next instruction,
which is already fetched, is discarded,
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
by a 2-word instruction.
INCFSZ
INCFSZ
:
:
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
f [,d [,a]]
ffff
CNT
destination
operation
operation
operation
Write to
PIC18F2331/2431/4331/4431
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=

=
=
=
register ‘f’
operation
operation
operation
Increment f, Skip if Not 0
[ label ]
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest,
skip if result  0
None
The contents of register, ‘f’, are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register, ‘f’.
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded, and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
3 cycles if skip and followed
by a 2-word instruction.
INFSNZ
INFSNZ
10da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39616D-page 305
f [,d [,a]]
REG
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff