PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 114

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
TABLE 11-1:
DS39616D-page 114
RA0/AN0
RA1/AN1
RA2/AN2/V
CAP1/INDX
RA3/AN3/V
CAP2/QEA
RA4/AN4/CAP3/
QEB
RA5/AN5/LVDIN
OSC2/CLKO/RA6
Legend:
OSC1/CLKI/RA7
Pin
REF
REF
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
-/
+/
PORTA I/O SUMMARY
Function
LVDIN
V
OSC2
CLKO
OSC1
V
CAP1
CAP2
CAP3
INDX
QEA
QEB
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
AN4
RA5
AN5
RA6
RA7
REF
REF
+
-
Setting
TRIS
0
1
1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
x
x
0
1
x
x
0
1
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input is enabled.
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input is enabled.
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog input is enabled.
A/D Input Channel 2. Default input configuration on POR.
A/D voltage reference low input.
Input Capture Pin 1. Disabled when analog input is enabled.
Quadrature Encoder Interface index input pin. Disabled when analog
input is enabled.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input is enabled.
A/D Input Channel 3. Default input configuration on POR.
A/D voltage reference high input.
Input Capture Pin 2. Disabled when analog input is enabled.
Quadrature Encoder Interface Channel A input pin. Disabled when
analog input is enabled.
LATA<4> data output; not affected by analog input.
PORTA<4> data input; disabled when analog input is enabled.
A/D Input Channel 4. Default input configuration on POR.
Input Capture Pin 3. Disabled when analog input is enabled.
Quadrature Encoder Interface Channel B input pin. Disabled when
analog input is enabled.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input is enabled.
A/D Input Channel 5. Default configuration on POR.
Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
Main oscillator input connection.
Main clock input connection.
LATA<7> data output. Disabled in external oscillator modes.
PORTA<7> data input. Disabled in external oscillator modes.
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
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