PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 46

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
4.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
TABLE 4-2:
DS39616D-page 46
Note 1:
is not stopped; and
HS or HSPLL modes.
Primary Device Clock
2:
3:
4:
(PRI_IDLE mode)
Before Wake-up
Clock Source
(Sleep mode)
INTOSC
T
rently with any other required delays (see
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
T1OSC
None
(Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concur-
is the Oscillator Start-up Timer (Parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
PLL
.
IOBST
After Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(Parameter 39), the INTOSC stabilization period.
(2)
(2)
(2)
(2)
Section 4.4 “Idle
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
rc
is the PLL Lock-out Timer (Parameter F12); it is
, following the wake event, is still required when
Modes”).
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST
None
CSD
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(1)
(3)
(1)
(3)
(1)
(3)
(1)
rc
(4)
rc
rc
(4)
(3)
(3)
(3)
 2010 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS