PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 147

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

16.4
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against the TMR1
register pair value. When a match occurs, the RC2/
CCP1 (RC1/CCP2) pin:
• is driven high
• is driven low
• toggles output (high-to-low or low-to-high)
• remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M<3:0> (CCP2M<3:0>). At the same time,
interrupt flag bit CCP1IF (CCP2IF) is set.
16.4.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISC bit.
FIGURE 16-2:
 2010 Microchip Technology Inc.
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the RC1 or RC2 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Special Event Trigger will:
RC2/CCP1 Pin
RC1/CCP2 Pin
Reset Timer1, but not set Timer1 interrupt flag bit
and set bit, GO/DONE (ADCON0<1>), which starts an A/D conversion (CCP2 only)
Output Enable
Output Enable
COMPARE MODE OPERATION BLOCK DIAGRAM
TRISC<1>
TRISC<2>
Q
Q
R
R
S
S
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
PIC18F2331/2431/4331/4431
Mode Select
Mode Select
Output
Output
Logic
Logic
Set Flag CCP2IF bit
Set Flag CCP1IF bit
Match
Match
16.4.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
16.4.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
16.4.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The Special Event Trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The Special Event Trigger output of CCP2 resets the
TMR1 register pair. Additionally, the CCP2 Special
Event Trigger will start an A/D conversion if the A/D
module is enabled.
Note:
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The Special Event Trigger from the CCP2
module will not set the Timer1 interrupt
flag bit.
CCPR1H CCPR1L
CCPR2H CCPR2L
TMR1H
Comparator
Comparator
DS39616D-page 147
TMR1L