PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 49

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

5.2
The MCLR pin can trigger an external Reset of the
device by holding the pin low. These devices have a
noise filter in the MCLR Reset path that detects and
ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the Watchdog Timer.
In PIC18F2331/2431/4331/4431 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. For more information, see
“PORTE, TRISE and LATE
5.3
A Power-on Reset pulse is generated on-chip when-
ever V
the device to start in the initialized state when V
adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to V
eliminate external RC components usually needed to
create a Power-on Reset delay. The minimum rise rate
for V
time, see
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (such
as voltage, frequency and temperature) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a POR occurs and does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
 2010 Microchip Technology Inc.
Note:
DD
DD
is specified (Parameter D004). For a slow rise
Master Clear (MCLR)
Power-on Reset (POR)
Figure
rises above a certain threshold. This allows
The following decoupling method is
recommended:
1. A 1 F capacitor should be connected
2. A
across AV
connected across V
5-2.
similar
DD
and AV
Registers”.
capacitor
DD
SS
.
and V
should
Section 11.5
DD
SS
. This will
PIC18F2331/2431/4331/4431
.
DD
be
is
FIGURE 5-2:
5.4
A Configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset
circuitry. If V
through D005F) for greater than T
the brown-out situation will reset the chip. A Reset may
not occur if V
The chip will remain in Brown-out Reset until V
above V
invoked after V
the chip in Reset for an additional time delay T
(Parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay. Enabling
the Brown-out Reset does not automatically enable the
PWRT.
Note 1: External Power-on Reset circuit is
V
BOR
2: R < 40 k is recommended to make
3: R1  1 k will limit any current flowing
DD
Brown-out Reset (BOR)
D
. If the Power-up Timer is enabled, it will be
required only if the V
too slow. The diode, D, helps discharge
the capacitor quickly when V
down.
sure that the voltage drop across R does
not
specification.
into MCLR from external capacitor, C, in
the event of MCLR/V
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
DD
DD
V
DD
DD
falls below V
falls below V
R
violate
DD
C
rises above V
DD
rises above V
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
drops below V
R1
the
BOR
BOR
DD
DD
device’s
PIC18FXXXX
BOR
MCLR
PP
BOR
power-up slope is
for less than T
(Parameter D005A
POWER-UP)
BOR
DS39616D-page 49
pin breakdown,
; it then will keep
(Parameter 35),
, the Power-up
BOR
DD
electrical
powers
while the
DD
PWRT
rises
BOR
.