PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 112

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
10.6
External interrupts on the INT0, INT1 and INT2 pins are
edge-triggered. If the corresponding INTEDGx bit in the
INTCON2 register is set (= 1), the interrupt is triggered
by a rising edge. If the bit is clear, the trigger is on the
falling edge.
When a valid edge appears on the INTx pin, the corre-
sponding flag bit, INTxIF, is set. This interrupt can be
disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from the Idle or Sleep modes if bit,
INTxIE, was set prior to going into those modes. If the
Global Interrupt Enable bit, GIE, is set, the processor
will branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).
There is no priority bit associated with INT0. It is
always a high-priority interrupt source.
EXAMPLE 10-1:
DS39616D-page 112
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTx Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
10.7
In 8-bit mode (which is the default), an overflow
(FFh  00h) in the TMR0 register will set flag bit,
TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h)
in the TMR0H:TMR0L registers will set flag bit,
TMR0IF. The interrupt can be enabled/disabled by
setting/clearing enable bit, TMR0IE (INTCON<5>).
Interrupt priority for Timer0 is determined by the value
contained in the interrupt priority bit, TMR0IP
(INTCON2<2>). See
for further details.
10.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
10.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see
“Fast Register
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 10-1
and BSR registers during an Interrupt Service Routine.
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
saves and restores the WREG, STATUS
Stack”), the user may need to save the
Section 12.0 “Timer0 Module”
 2010 Microchip Technology Inc.
Section 6.1.3