PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 188

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
18.6.2
The
double-buffered to allow glitchless updates of the PWM
outputs. For each duty cycle block, there is a Duty
Cycle Buffer register that is accessible by the user and
a second Duty Cycle register that holds the actual
compare value used in the present PWM period.
In Edge-Aligned PWM Output mode, a new duty cycle
value will be updated whenever a PTMR match with the
PTPER register occurs and PTMR is reset as shown in
Figure
are automatically loaded into the Duty Cycle registers
when the PWM time base is disabled (PTEN = 0).
When the PWM time base is in the Continuous
Up/Down Count mode, new duty cycle values will be
updated when the value of the PTMR register is zero
and the PWM time base begins to count upwards. The
contents of the duty cycle buffers are automatically
loaded into the Duty Cycle registers when the PWM
time base is disabled (PTEN = 0).
the timings when the duty cycle update occurs for the
Continuous Up/Down Count mode. In this mode, up to
one entire PWM period is available for calculating and
loading the new PWM duty cycle before changes take
effect.
When the PWM time base is in the Continuous
Up/Down Count mode with double updates, new duty
cycle values will be updated when the value of the
PTMR register is zero and when the value of the PTMR
register matches the value in the PTPER register. The
contents of the duty cycle buffers are automatically
loaded into the Duty Cycle registers during both of the
previously described conditions.
the duty cycle updates for Continuous Up/Down Count
mode with double updates. In this mode, only up to half
of a PWM period is available for calculating and loading
the new PWM duty cycle before changes take effect.
FIGURE 18-13:
DS39616D-page 188
18-12. Also, the contents of the duty cycle buffers
four
DUTY CYCLE REGISTER BUFFERS
PWM
PWM Output
PTMR Value
DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE
Duty
Cycle
Figure 18-14
Figure 18-13
registers
Duty Cycle Value Loaded from Buffer Register
shows
shows
are
18.6.3
Edge-aligned PWM signals are produced by the
module when the PWM time base is in the
Free-Running mode or the Single-Shot mode. For
edge-aligned PWM outputs, the output for a given
PWM channel has a period specified by the value
loaded in PTPER and a duty cycle specified by the
appropriate Duty Cycle register (see
The PWM output is driven active at the beginning of the
period (PTMR = 0) and is driven inactive when the
value in the Duty Cycle register matches PTMR. A new
cycle is started when PTMR matches the PTPER as
explained in the PWM period section.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 18-12:
PTPER
Active at
Beginning
of Period
PDCx
PDCx
(new)
New Value Written to Duty Cycle Buffer
(old)
0
PTMR
Value
EDGE-ALIGNED PWM
Duty Cycle
Period
EDGE-ALIGNED PWM
 2010 Microchip Technology Inc.
New Duty Cycle Latched
Figure
18-12).