PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 249

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

21.2
The A/D module has a 4-level result buffer with an
address range of 0 to 3, enabled by setting the FIFOEN
bit in the ADCON1 register. This buffer is implemented
in a circular fashion, where the A/D result is stored in
one location and the address is incremented. If the
address is greater than 3, the pointer is wrapped back
around to 0. The result buffer has a Buffer Empty Flag,
BFEMT, indicating when any data is in the buffer. It also
has a Buffer Overflow Flag, BFOVFL, which indicates
when a new sample has overwritten a location that was
not previously read.
Associated with the buffer is a pointer to the address for
the next read operation. The ADPNT<1:0> bits
configure the address for the next read operation.
These bits are read-only.
The Result Buffer also has a configurable interrupt
trigger level that is configured by the ADRS<1:0> bits.
The user has three selections: interrupt flag set on
every write to the buffer, interrupt on every second write
to the buffer, or interrupt on every fourth write to the
buffer. ADPNT<1:0> are reset to ‘00’ every time a
conversion sequence is started (either by setting the
GO/DONE bit or on a trigger).
EQUATION 21-1:
EQUATION 21-2:
 2010 Microchip Technology Inc.
T
V
or
T
ACQ
Note:
C
HOLD
=
=
A/D Result Buffer
=
=
When right justified, reading ADRESL
increments the ADPNT<1:0> bits. When
left justified, reading ADRESH increments
the ADPNT<1:0> bits.
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
T
AMP
(V
-(C
REF
HOLD
+ T
– (V
C
ACQUISITION TIME
MINIMUM A/D HOLDING CAPACITOR CHARGING TIME
)(R
+ T
REF
IC
COFF
/2048)) • (1 – e
+ R
SS
+ R
S
) ln(1/2048)
(-T
C
PIC18F2331/2431/4331/4431
/C
HOLD
(R
IC
+ R
SS
+ R
S
))
21.3
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in
source impedance (R
switch (R
required to charge the capacitor C
switch (R
(V
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To
Equation 21-1
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 21-1
required acquisition time T
converter module is fully powered up at the outset and
therefore, the amplifier settling time, T
This calculation is based on the following application
system assumptions:
C
Rs
Conversion Error
V
Temperature
V
)
DD
HOLD
HOLD
DD
Note:
). The source impedance affects the offset voltage
calculate
A/D Acquisition Requirements
SS
SS
) impedance varies over the device voltage
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
) impedance directly affect the time
shows the calculation of the minimum
may be used. This equation assumes
the
=
=

=
=
=
S
minimum
) and the internal sampling
9 pF
100
1/2 LSb
5V  Rss = 6 k
50°C (system max.)
0V @ time = 0
ACQ
HOLD
. In this case, the
HOLD
DS39616D-page 249
acquisition
) must be allowed
Figure
AMP
. The sampling
, is negligible.
21-2. The
time,