PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 156

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
When in Counter mode, the counter must be
configured
(T5SYNC = 0). When configured in Asynchronous
mode, the IC module will not work properly.
FIGURE 17-4:
DS39616D-page 156
Note 1: Input capture
Note 1: TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on the Q1 rising edge.
TMR5
CAP1 Pin
CAP1BUF
TMR5 Reset
Instruction
Execution
2: When the Input Capture mode is
3: During IC mode changes, the prescaler
(1)
2: IC1 is configured in Edge Capture mode (CAP1M<3:0> = 0010) with the time base reset upon edge capture
3: TMR5 value is latched by CAP1BUF on T
4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used with the input capture, it is active
5: TMR5 Reset pulse is disabled by clearing the CAP1REN bit (e.g., BCF CAP1CON, CAP1REN).
(2)
(cleared) when the input capture module
is disabled (CAPxM = 0000).
changed, without first disabling the
module and entering the new Input Cap-
ture mode, a false interrupt (or Special
Event Trigger on IC1) may be generated.
The user should either: (1) disable the
input capture before entering another
mode, or (2) disable IC interrupts to avoid
false interrupts during IC mode changes.
count will not be cleared, therefore, the
first capture in the new IC mode may be
from the non-zero prescaler.
(3)
(CAP1REN = 1) and no noise filter.
the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated
with the incremented value of the time base on the next T
Note 4 when Reset occurs).
immediately after the time base value is captured.
as
(4)
OSC
MOVWF CAP1CON
the
Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
EDGE CAPTURE MODE TIMING
0012
synchronous
prescalers are reset
0013
ABCD
counter
0014
CY
only
. In the event that a write to TMR5 coincides with an input capture event,
0015
0000
17.1.1
In this mode, the value of the time base is captured
either on every rising edge, every falling edge, every
4th rising edge, or every 16th rising edge. The edge
present on the input capture pin (CAP1, CAP2 or
CAP3) is sampled by the synchronizing latch. The
signal is used to load the Input Capture Buffer (ICxBUF
register) on the following Q1 clock (see
Consequently, Timer5 is either reset to ‘0’ (Q1
immediately following the capture event) or left free
running, depending on the setting of the Capture Reset
Enable bit, CAPxREN, in the CAPxCON register.
CY
Note:
clock edge when the capture event takes place (see
0001
0016
BCF CAP1CON, CAP1REN
EDGE CAPTURE MODE
On the first capture edge following the
setting of the Input Capture mode (i.e.,
MOVWF CAP1CON), Timer5 contents are
always captured into the corresponding
Input Capture Buffer (i.e., CAPxBUF).
Timer5 can optionally be reset; however,
this is dependent on the setting of the
Capture Reset Enable bit, CAPxREN (see
Figure
0002
17-4).
 2010 Microchip Technology Inc.
0000
0003
0001
Figure
0002
Note 5
0002
17-4).