AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 719
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AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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35.8.6
35.8.6.1
6355B–ATARM–21-Jun-10
READ_SINGLE_BLOCK Operation using DMA Controller
Block Length is Multiple of 4
7. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully completed.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
5. Program HSMCI_DMA register with the following fields:
6. Issue a READ_SINGLE_BLOCK command.
7. Program the DMA controller.
i.
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– ROPT field is set to 0.
– OFFSET field is set to 0.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
e. The DMAC_DADDRx register for channel x must be word aligned.
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
– DST_INCR is set to INCR.
– SRC_INCR is set to INCR.
– FC field is programmed with peripheral to memory flow control mode.
– both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
h. Program DMAC_CFGx register for channel x with the following field’s values:
was previously set to false.
DMA controller is able to prefetch data and write HSMCI simultaneously.
Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting
for request.
reading the DMAC_EBCISR register.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
HSMCI Host Controller.
AT91SAM9M10
719
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