AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 253
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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Figure 22-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
6355B–ATARM–21-Jun-10
COMMAND
DQS[1:0]
BA[1:0]
DM1:0]
D[15:0]
A[12:0]
SDClK
NOP
0
3
READ
1
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from differ-
ent masters to the SDRAM device in a round-robin manner. If two or more master requests arise
at the same time, the master with the lowest number is serviced first, then the others are ser-
viced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput
for the SDRAM device, arbitration may only take place during the following cycles:
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For
4. Anticipated Access: When an anticipate read access is done while current access is
Anticipate command, Precharge/Active Bank 2
bursts of defined length, predicted end of burst matches the size of the transfer. For
bursts of undefined length, predicted end of burst is generated at the end of each four
beat boundary inside the INCR transfer.
not complete, the arbitration scheme can be changed if the anticipated access is not
the next access serviced by the arbitration scheme.
PRECH
Read access in Bank 1
2
Trp
NOP
Da
Db
ACT
Dc
Dd
READ
1
De
Df
Dg
AT91SAM9M10
Dh
NOP
Di
Dj
Dk
Dl
253
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