AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1313
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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46.11.1
Name:
Access:
• PPE: Post-processor Standalone Enable
0: Disables post-processor.
1: Enables post-processor.
Setting this bit high will start the post-processing operation. Hardware will reset this bit when a picture is processed.
• PIPE: Decoder Post-processing Pipeline Enable
0: Disables the pipeline.
1: Enables the pipeline.
When high, post-processing is performed in pipeline with decoder. When low, post-processor is processing different picture
than the decoder.
• ID: Interrupt Disable
0: Enables Interrupts for post-processor.
1: Disables Interrupts for post-processor.
When high, there will be no interrupts issued by the post-processor. Polling must be used to see the hardware status.
• ISET: Post-processor Interrupt Set
0: Clears the post-processor Interrupt.
Software will reset this after the interrupt is handled.
1: Set the post-processor interrupt.
This bit drives the interrupt line, OR gated with the decoder interrupt bit.
Software will reset this after the interrupt is handled. The interrupt line is not used if the interrupt disable bit for post-proces-
sor is high.
• PPR: Post-processor Ready
0: Post processing in progress.
1: Post-processor is ready.
If decoder and post-processor are running in pipeline, this bit is not used.
6355B–ATARM–21-Jun-10
31
23
15
–
–
–
7
–
Post-Processor Interrupt Register
30
22
14
VDEC_PPIR
Read-write
–
–
–
6
–
BE
29
21
13
–
–
5
–
PPR
28
20
12
ID
–
–
4
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
AT91SAM9M10
PIPE
25
17
–
–
9
–
1
ISET
PPE
24
16
–
–
8
0
1313
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