AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 943
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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40.10.2
6355B–ATARM–21-Jun-10
Touch Screen Mode
If the PDC is enabled, all the converted data are transferred contiguously in the memory buffer.
The bit LOWRES defines which resolution is used, either 8-bit or 10-bit, and thus the width of the
PDC memory buffer.
Writing TSAMOD to “Touch Screen Only Mode” automatically enables the touch screen pins as
analog inputs, and thus disables the digital function of the corresponding pins.
In Touch Screen Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are auto-
matically activated and the bits CH0 to CH3 are automatically set in the
Status
The remaining channels can be either enabled or disabled by the user and their conversions are
performed at the end of each touch screen sequence.
The resolution is forced to 10 bits, regardless of the LOWRES bit setting.
At each trigger, if the bit PRES in
is performed to measure only position.
The resulting buffer is 16 bits wide and its structure stored in memory is:
5. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1
6. If Channel 2 is enabled, convert Channel 2 and store result in both TSADCC_CDR2
7. If Channel 3 is enabled, convert Channel 3 and store result in both TSADCC_CDR3
8. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
9. If SLEEP is set, sleep down the ADC cell.
1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
2. Close the switches on the inputs X
3. Convert Channel X
4. Close the switches on the inputs X
5. Convert Channel X
6. Close the switches on the inputs X
7. Convert Channel Y
8. Close the switches on the inputs Y
9. Convert Channel Y
10. Close the switches on the inputs Y
11. Convert Channel Y
12. Close the switches on the inputs Y
13. Convert Channel X
14. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
15. If SLEEP is set, sleep down the ADC cell.
and TSADCC_LCDR.
and TSADCC_LCDR.
and TSADCC_LCDR.
responding TSADCC_CDRx and TSADCC_LCDR.
result in both TSADCC_CDR0 and TSADCC_LCDR.
result in both TSADCC_CDR1 and TSADCC_LCDR.
result in both TSADCC_CDR2 and TSADCC_LCDR.
result in both TSADCC_CDR3 and TSADCC_LCDR.
responding TSADCC_CDRx and TSADCC_LCDR.
Register”.
P
P
P
P
M
M
, subtract TSADCC_CDR1 from the result and store the subtraction
, subtract TSADCC_CDR1 from the result and store the subtraction
, subtract TSADCC_CDR3 from the result and store the subtraction
, subtract TSADCC_CDR3 from the result and store the subtraction
and store the result in TSADCC_CDR1.
and store the result in TSADCC_CDR3.
“TSADCC Mode Register”
P
P
P
P
P
P
and X
and X
and X
and Y
and Y
and Y
M
M
M
M
M
M
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
is disabled, the following sequence
AT91SAM9M10
“TSADCC Channel
943
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