AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 42
AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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9.5
42
CP15 Coprocessor
AT91SAM9M10
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
To control these features, CP15 provides 16 additional registers. See
Table 9-5.
Notes:
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
• TCM
• MMU
• Other system options
Register
1. Register locations 0,5, and 13 each provide access to more than one register. The register
2. Register location 9 provides access to more than one register. The register accessed depends
10
11
12
13
13
14
15
0
0
0
1
2
3
4
5
5
6
7
8
9
9
accessed depends on the value of the opcode_2 field.
on the value of the CRm field.
CP15 Registers
Name
ID Code
Cache type
TCM status
Control
Translation Table Base
Domain Access Control
Reserved
Data fault Status
Instruction fault status
Fault Address
Cache Operations
TLB operations
cache lockdown
TCM region
TLB lockdown
Reserved
Reserved
FCSE PID
Context ID
Reserved
Test configuration
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
Read/Unpredictable
Read/Unpredictable
Read/Unpredictable
Read/write
Read/write
Read/write
None
Read/write
Read/write
Read/write
Read/Write
Read/write
Read/write
Read/write
None
None
Read/write
Read/Write
None
Read/Write
Read/Write
Unpredictable/Write
Table
9-5.
6355B–ATARM–21-Jun-10
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