AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 260

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.7.1
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini-
tialize the SDRAM device and to activate deep power-down mode.
260
MODE
000
001
010
011
100
101
110
111
31
23
15
–
–
–
7
–
AT91SAM9M10
DDRSDRC Mode Register
Description
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed
by a write to the SDRAM.
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this
mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a
write to the SDRAM.
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of
the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM.
The write in the SDRAM must be done in the appropriate bank.
Deep power mode: Access to deep power-down mode
Reserved
30
22
14
DDRSDRC_MR
Read-write
See
–
–
–
6
–
Table 22-9
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
6355B–ATARM–21-Jun-10
275.
24
16
–
–
8
–
0