MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 88

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

2.4.3 Pin State During Reset
2.4.4 Power-On Reset and Hard Reset
2.4.5 Pull-Up and Pull-Down Enable and Disable for 5-V Only Pins
MPC555
USER’S MANUAL
Bit(s)
9:31
7
8
During reset, the functionality of some pins is undetermined. Their functionality is
based on the bits in the SIUMCR. Since the SIUMCR bits are undetermined during re-
set, there is no way of predicting how the pins will function. However, the pins must not
cause any spurious conditions or consume an excessive amount of power during re-
set. To prevent these conditions, the pins need to have a defined reset state.
4
All pins are initialized to a “reset state” during reset. This state remains active until re-
set is negated or until software disables the pull-up or pull-down device based on the
pin functionality. Upon assertion of the corresponding bits in the pin control registers
and negation of reset, the pin acquires the functionality that was programmed.
Power-on reset and hard reset affect the functionality of the pins out of reset. (During
soft reset, the functionality of the pins is unaltered.) Upon assertion of the power-on
reset signal (PORESET) the functionality of the pin is not yet known. The pull-up or
pull-down resistors are enabled. The reset configuration word configures the system,
and towards the end of reset the pin functionality is known. Based upon pin function-
ality, the pull-up or pull-down devices are either disabled immediately at the negation
of reset or remain enabled.
Hard reset can occur at any time, and there may be a bus cycle pending. For this rea-
son, the bits in PDMCR that control the enabling and disabling of the pull-up or pull-
down resistors in the pads are set or reset synchronously. (PORESET affects these
bits asynchronously.) This causes the pull-up or pull-down resistors to be enabled at
a time when they do not cause contention on the pins and are disabled before they
can cause any contention on the pins.
For 5-V only pins, the enabling and disabling of the pull-up and pull-down devices is
controlled by the PRDS bit in PDMCR. If the bit is negated, the devices are active. If
the bit is asserted, the devices are inactive.
describes the reset state of the pins based on pin functionality.
FTPU_PU
/
SPRDS
MPC556
Name
—
The SPRDS bit is used to enable or disable the weak pull-up/pull-down devices in special 3-V
only bus pads.
this bit affects the pins see
0 = Enable pull-up/pull-down devices
1 = Disable pull-up/pull-down devices
Follow TPU Pull-Up — Controls the pull-up devices for all T2CLK pins. FTPU_PU is only avail-
able on mask set K62N and later.
0 = Pull-ups are active when the pins are defined as inputs
1 = Pull-ups for the TPU T2CLK pins are enabled or disabled based on the state of PRDS
Reserved
Table 2-3 PDMCR Bit Descriptions (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2-4
Go to: www.freescale.com
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
illustrates which pins are affected by SPRDS. For more details on how
2.4.7 Special Pull Resistor Disable Control
Description
(SPRDS).
MOTOROLA
Table 2-
2-30