MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 449

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
8:15
3:7
0
1
2
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Name
SSE1
CIE1
PIE1
MQ1
—
Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The inter-
rupt request is generated when the conversion is complete for the last CCW in queue 1.
0 = Queue 1 completion interrupts disabled
1 = Generate an interrupt request after completing the last CCW in queue 1
Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt re-
quest is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 1 pause interrupts disabled
1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set
Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs.
The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the sin-
gle-scan queue operating mode. The single-scan enable bit can be written as a one or a zero,
but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 1. The QADC64 clears SSE1 when the single-scan is complete.
Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1.
13-13
Reserved
shows the different queue 1 operating modes.
Freescale Semiconductor, Inc.
Table 13-12 QACR1 Bit Descriptions
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Description
MOTOROLA
Table
13-37