MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet

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... Freescale Semiconductor, Inc. MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000  Copyright 2000 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. MPC555 / MPC556 USER’S MANUAL Revised 15 October 2000  Copyright 2000 MOTOROLA; All Rights Reserved For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 MPC555 / MPC556 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1 RISC MCU Central Processing Unit (RCPU 1-2 1.2.2 Four-Bank Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.3 U-Bus System Interface Unit (USIU 1-3 1.2.4 Flexible Memory Protection Unit 1-3 1 ...

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... Freescale Semiconductor, Inc. Paragraph Number 2.3.1.16 TEA 2-15 2.3.1.17 RSTCONF/TEXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1. 2-16 2.3.1.19 BI/STS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.20 CS[0: 2-16 2.3.1.21 WE[0:3]/BE[0:3]/AT[0: 2-16 2.3.1.22 PORESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.23 HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.24 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.25 SGPIOC[6]/FRZ/PTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.26 SGPIOC[7]/IRQOUT/LWP[ 2-18 2 ...

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... Freescale Semiconductor, Inc. Paragraph Number 2.3.3.6 VFLS[0:1]/MPIO32B[3: 2-23 2.3.3.7 MPIO32B[5:15 2-24 2.3.4 TPU_A/TPU_B PADS 2-24 2.3.4.1 TPUCH[0:15]_[A: 2-24 2.3.4.2 T2CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5 QADC_A/QADC_B PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5.1 ETRIG[1: 2-24 2.3.5.2 AN[0]/ANW/PQB[0]_[A:B 2-24 2.3.5.3 AN[1]/ANX/PQB[1]_[A: 2-24 2.3.5.4 AN[2]/ANY/PQB[2]_[A: 2-25 2 ...

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... Freescale Semiconductor, Inc. Paragraph Number 2.4.6.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.4.7 Special Pull Resistor Disable Control (SPRDS 2-31 2.4.8 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.5 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.1 Pad Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.2 Three-Volt Output Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.5.2.1 Type A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.5.2.2 Type B Interface (Clock Pad 2-39 2 ...

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... Freescale Semiconductor, Inc. Paragraph Number 3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 Independent Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.1 Branch Processing Unit (BPU 3-5 3.4.2 Integer Unit (IU 3-5 3.4.3 Load/Store Unit (LSU 3-6 3.4.4 Floating-Point Unit (FPU 3-6 3.5 Levels of the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.6 RCPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3 ...

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... Freescale Semiconductor, Inc. Paragraph Number 3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3.12 Instruction Timing 3-36 3.13 PowerPC User Instruction Set Architecture (UISA 3-38 3.13.1 Computation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.2 Reserved Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.3 Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.5 The Branch Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3 ...

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... Freescale Semiconductor, Inc. Paragraph Number 3.15.4.2 Machine Check Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.15.4.3 Data Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.15.4.4 Instruction Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.5 Alignment Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt . . . . . . . . . . . . . . . . . 3-46 3.15.4.7 Illegal Instruction Type Program Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.8 Privileged Instruction Type Program interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3 ...

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... Freescale Semiconductor, Inc. Paragraph Number 4.6 Burst Buffer Programming Model 4-20 4.6.1 Region Base Address Registers 4-21 4.6.2 Region Attribute Registers MI_RA[0:3] Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.6.3 Global Region Attribute Register Description (MI_GRA 4-23 4.6.4 BBC Module Configuration Register (BBCMCR 4-24 UNIFIED SYSTEM INTERFACE UNIT 5 ...

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... Freescale Semiconductor, Inc. Paragraph Number 6.13.3.1 System Protection Control Register (SYPCR 6-26 6.13.3.2 Software Service Register (SWSR 6-26 6.13.3.3 Transfer Error Status Register (TESR 6-27 6.13.4 System Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.1 Decrementer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.2 Time Base SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.3 Time Base Reference Registers 6-29 6 ...

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... Freescale Semiconductor, Inc. Paragraph Number 8.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1 Frequency Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.2 Skew Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.3 Pre-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.4 PLL Block Diagram 8-4 8.3.5 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4 System Clock During PLL Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5 Low-Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8 ...

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... Freescale Semiconductor, Inc. Paragraph Number 8.12.3 Change of Lock Interrupt Register (COLIR 8-35 8.12.4 VDDSRAM Control Register (VSRMCR 8-36 9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.5 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9 ...

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... Freescale Semiconductor, Inc. Paragraph Number 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 Memory Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.1 Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.2 Port Size Configuration 10-5 10.2.3 Write-Protect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.4 Address and Address Space Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.5 Burst Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.3 Chip-Select Timing 10-6 10 ...

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... Freescale Semiconductor, Inc. Paragraph Number 11.6.2 L2U Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.6.3 Reserved Location (Bus) and Possible Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7 L-Bus Show Cycle Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.1 Programming Show Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.2 Performance Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.3 Show Cycle Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.4 L-Bus Write Show Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11 ...

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... Freescale Semiconductor, Inc. Paragraph Number 13.3.4 Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.7 Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.8 External Digital Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.9 Digital Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.4 QADC64 Bus Interface 13-6 13 ...

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... Freescale Semiconductor, Inc. Paragraph Number 13.12.6 QADC64 Control Register 0 (QACR0 13-35 13.12.7 QADC64 Control Register 1 (QACR1 13-36 13.12.8 QADC64 Control Register 2 (QACR2 13-38 13.12.9 QADC64 Status Register 0 (QASR0 13-40 13.12.10 QADC64 Status Register 1 (QASR1 13-42 13.12.11 Conversion Command Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 13 ...

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... Freescale Semiconductor, Inc. Paragraph Number 14.7.5.1 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34 14.7.5.2 Baud Rate Selection 14-34 14.7.5.3 Delay Before Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14.7.5.4 Delay After Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14.7.5.5 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36 14.7.5.6 Peripheral Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36 14.7.5.7 Master Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37 14.7.6 Slave Mode 14-37 14 ...

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... Freescale Semiconductor, Inc. Paragraph Number 14.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . 14-73 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1) 15.1 MIOS1 Features 15-1 15.2 Submodule Numbering, Naming and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3 MIOS1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.5 MIOS1 Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15 ...

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... Freescale Semiconductor, Inc. Paragraph Number 15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR 15-28 15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR 15-28 15.13 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM 15-30 15.13.1 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) Registers 15-30 15.13.1.1 MPIOSM Data Register (MPIOSMDR 15-30 15 ...

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... Freescale Semiconductor, Inc. Paragraph Number 16.4.2 TouCAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.4.3 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.4.3.1 Transmit Message Buffer Deactivation 16-13 16.4.3.2 Reception of Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.4.4 Receive Process 16-13 16.4.4.1 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.4.4.2 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16 ...

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... Freescale Semiconductor, Inc. Paragraph Number 17.3.2 Channel Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.3 Interchannel Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.4 Programmable Channel Service Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.6 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.7 TPU3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.3.8 Prescaler Control for TCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.3.9 Prescaler Control for TCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17 ...

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... Freescale Semiconductor, Inc. Paragraph Number 18.4.4 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.4.5 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.4.6 TPU3 Emulation Mode Operation 18-8 18.5 Multiple Input Signature Calculator (MISC 18-8 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 MPC555 / MPC556 CMF Features 19-2 19.1.2 Glossary of Terms for the CMF EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19 ...

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... Freescale Semiconductor, Inc. Paragraph Number 19.8.2 Censored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31 19.8.3 Device Modes and Censorship Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32 19.8.4 Setting and Clearing Censor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33 19.8.5 Switching the CMF EEPROM Censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35 19.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 19.9.1 E Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 PEE 19.9.2 FLASH Program/Erase Voltage Conditioning 19-37 19 ...

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... Freescale Semiconductor, Inc. Paragraph Number 21.3.1.5 Ignore First Match 21-15 21.3.1.6 Generating Six Compare Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.3.2 Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.3.2.1 Load/Store Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.3.3 Watchpoint Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.3.3.1 Trap Enable Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.4 Development System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.4.1 Debug Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21 ...

Page 26

... Freescale Semiconductor, Inc. Paragraph Number 21.7.6 I-Bus Support Control Register 21-47 21.7.7 L-Bus Support Control Register 21-49 21.7.8 L-Bus Support Control Register 21-50 21.7.9 Breakpoint Counter A Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.7.10 Breakpoint Counter B Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.7.11 Exception Cause Register (ECR 21-53 21 ...

Page 27

... Freescale Semiconductor, Inc. Paragraph Number D.10 Multichannel Pulse-Width Modulation (MCPWM D-22 D.11 Fast Quadrature Decode TPU Function (FQD D-29 D.12 Period/Pulse-Width Accumulator (PPWA D-32 D.13 Output Compare (OC D-34 D.14 Pulse-Width Modulation (PWM D-36 D.15 Discrete Input/Output (DIO D-38 D.16 Synchronized Pulse-Width Modulation (SPWM D-40 D ...

Page 28

... Freescale Semiconductor, Inc. Paragraph Number G.7 DC Electrical Characteristics G-7 G.8 Oscillator and PLL Electrical Characteristics G-12 G.9 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-12 G.10 FLASH Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-13 G.10.1 Flash Module Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-14 G.10.2 Programming and Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-15 G.11 Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-16 G ...

Page 29

... Freescale Semiconductor, Inc. Figure LIST OF FIGURES Number 1-1 MPC555 / MPC556 Block Diagram ................................................................ 1-2 1-2 MPC555 / MPC556 Memory Map ................................................................... 1-6 1-3 MPC555 / MPC556 Internal Memory Map ...................................................... 1-7 2-1 MPC555 / MPC556 Case Dimensions and Packaging ................................... 2-2 2-2 MPC555 / MPC556 Pinout Data ..................................................................... 2-3 2-3 Type A Interface ...

Page 30

... Freescale Semiconductor, Inc. Figure Number 4-8 Examples of Instruction Layout in Memory ..................................................... 4-9 4-9 Generating Compressed Code Address for PowerPC Direct Branches ................................................................... 4-10 4-10 Extracting Direct Branch Target Address in the Decompressor ................... 4-11 4-11 Code Compression Process (Phase A) ........................................................ 4-12 4-12 Bounded Huffman Code Tree ....................................................................... 4-13 4-13 Code Decompression Process ...

Page 31

... Freescale Semiconductor, Inc. Figure Number 9-1 Input Sample Window ..................................................................................... 9-2 9-2 MPC555 / MPC556 Bus Signals ..................................................................... 9-3 9-3 Basic Transfer Protocol .................................................................................. 9-8 9-4 Basic Flow Diagram of a Single Beat Read Cycle .......................................... 9-9 9-5 Single Beat Read Cycle–Basic Timing–Zero Wait States ............................ 9-10 9-6 Single Beat Read Cycle– ...

Page 32

... Freescale Semiconductor, Inc. Figure Number 10-1 Memory Controller Function Within the USIU ............................................... 10-1 10-2 Memory Controller Block Diagram ................................................................ 10-2 10-3 MPC555 / MPC556 Simple System Configuration ....................................... 10-3 10-4 Bank Base Address and Match Structure ..................................................... 10-4 10-5 MPC555 / MPC556 GPCM–Memory Devices Interface ............................... 10-7 ...

Page 33

... Freescale Semiconductor, Inc. Figure Number 13-7 QADC64 Queue Operation with Pause ...................................................... 13-16 13-8 QADC64 Clock Subsystem Functions ........................................................ 13-26 13-9 QADC64 Clock Programmability Examples ............................................... 13-28 13-10 QADC64 Interrupt Flow Diagram ................................................................ 13-30 13-11 Interrupt Levels on IRQ with ILBS .............................................................. 13-31 13-12 QADC64 Conversion Queue Operation ..................................................... 13-44 14-1 QSMCM Block Diagram ...

Page 34

... Freescale Semiconductor, Inc. Figure Number 16-3 Extended ID Message Buffer Structure ........................................................ 16-4 16-4 Standard ID Message Buffer Structure ......................................................... 16-4 16-5 Interrupt levels on IRQ with ILBS ............................................................... 16-20 16-6 TouCAN Message Buffer Memory Map ...................................................... 16-22 17-1 TPU3 Block Diagram .................................................................................... 17-1 17-2 TPU3 Interrupt Levels ................................................................................... 17-5 17-3 TCR1 Prescaler Control ...

Page 35

... Freescale Semiconductor, Inc. Figure Number 22-6 Observe-Only Input Pin Cell (I.Obs) ............................................................. 22-8 22-7 Output Control Cell (IO.CTL) ........................................................................ 22-9 22-8 General Arrangement of Bidirectional Pin Cells ........................................... 22-9 D-1 TPU3 Memory Map ........................................................................................D-1 D-2 PTA Parameters .............................................................................................D-5 D-3 QOM Parameters ...........................................................................................D-7 D-4 TSM Parameters — Master Mode ..................................................................D-9 D-5 TSM Parameters — ...

Page 36

... Freescale Semiconductor, Inc. Figure Number E-7 LC Filter Example (Alternative) ...................................................................... E-7 E-8 PLL Off-Chip Capacitor Example ................................................................... E-7 G-1 CLKOUT Timing .......................................................................................... G-16 G-2 External Clock Timing ................................................................................. G-23 G-3 Synchronous Output Signals Timing ........................................................... G-24 G-4 Synchronous Active Pull-Up and Open Drain Outputs Signals Timing ....... G-25 G-5 Synchronous Input Signals Timing ...

Page 37

... Freescale Semiconductor, Inc. Figure Number Timing Diagram ........................................................................................... G-63 G-40 MMCSM Clock Pin to Counter Bus Increment Timing Diagram ........................................................................................... G-63 G-41 MMCSM Load Pin to Counter Bus Reload Timing Diagram ....................... G-63 G-42 MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram ....................................................................... G-64 G-43 MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram ...

Page 38

... Freescale Semiconductor, Inc. Figure Number MPC555 / MPC555 USER’S MANUAL For More Information On This Product, LIST OF FIGURES Rev. 15 October 2000 Go to: www.freescale.com Page Number MOTOROLA xxxviii ...

Page 39

... Freescale Semiconductor, Inc. LIST OF TABLES Table Number 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA ........................................... 2-4 2-2 Pin Functionality Table .......................................................................................... 2-7 2-3 PDMCR Bit Descriptions..................................................................................... 2-29 2-4 Pin Reset State.................................................................................................... 2-32 2-5 Pad Groups Based on 3-V / 5-V Select ............................................................... 2-57 2-6 Pin Names and Abbreviations ............................................................................. 2-58 3-1 RCPU Execution Units ...

Page 40

... Freescale Semiconductor, Inc. Table Number 6-1 USIU Pins Multiplexing Control.............................................................................. 6-3 6-2 SGPIO Configuration ............................................................................................. 6-7 6-3 Priority of Interrupt Sources ................................................................................. 6-12 6-4 Decrementer Time-Out Periods........................................................................... 6-13 6-5 SIUMCR Bit Descriptions.................................................................................... 6-19 6-6 Debug Pins Configuration.................................................................................... 6-20 6-7 Debug Port Pins Configuration ............................................................................ 6-20 6-8 General Pins Configuration ...

Page 41

... Freescale Semiconductor, Inc. Table Number 9-3 Data Bus Contents for Write Cycles .................................................................... 9-30 9-4 Priority Between Internal and External Masters over External Bus ..................... 9-34 9-5 Burst Length and Order ....................................................................................... 9-36 9-6 BURST/TSIZE Encoding ..................................................................................... 9-37 9-7 Address Type Pins............................................................................................... 9-37 9-8 Address Types Definition..................................................................................... 9-38 9-9 Termination Signals Protocol ...

Page 42

... Freescale Semiconductor, Inc. Table Number 13-9 PORTQA, PORTQB Bit Descriptions ............................................................. 13-34 13-10 DDRQA Bit Descriptions............................................................................... 13-35 13-11 QACR0 Bit Descriptions ............................................................................... 13-36 13-12 QACR1 Bit Descriptions ............................................................................... 13-37 13-13 Queue 1 Operating Modes ............................................................................ 13-38 13-14 QACR2 Bit Descriptions ............................................................................... 13-39 13-15 Queue 2 Operating Modes ............................................................................ 13-40 13-16 QASR0 Bit Descriptions ...

Page 43

... Freescale Semiconductor, Inc. Table Number 15-2 MBISM Address Map......................................................................................... 15-8 15-3 MIOS1TPCR Bit Descriptions............................................................................ 15-9 15-4 MIOS1VNR Bit Descriptions .............................................................................. 15-9 15-5 MIOS1MCR Bit Descriptions ........................................................................... 15-10 15-6 MBISM Interrupt Registers Address Map ........................................................ 15-10 15-7 MIOS1LVL0 Bit Descriptions ........................................................................... 15-11 15-8 MIOS1LVL1 Bit Descriptions ........................................................................... 15-11 15-9 MCPSM Address Map ...

Page 44

... Freescale Semiconductor, Inc. Table Number 16-10 TouCAN Register Map................................................................................... 16-21 16-11 TCNMCR Bit Descriptions ............................................................................ 16-23 16-12 CANICR Bit Descriptions .............................................................................. 16-25 16-13 CANCTRL0 Bit Descriptions......................................................................... 16-25 16-14 RX MODE[1:0] Configuration......................................................................... 16-26 16-15 Transmit Pin Configuration ............................................................................ 16-26 16-16 CANCTRL1 Bit Descriptions.......................................................................... 16-27 16-17 PRESDIV Bit Descriptions ............................................................................ 16-28 16-18 CANCTRL2 Bit Descriptions ...

Page 45

... Freescale Semiconductor, Inc. Table Number 19-3 CMFTST Bit Descriptions .................................................................................. 19-8 19-4 CMF Programming Algorithm (v6 and Later)..................................................... 19-8 19-5 CMF Erase Algorithm (v6) ................................................................................. 19-9 19-6 CMFCTL Bit Descriptions ................................................................................ 19-10 19-7 EEPROM Array Addressing............................................................................. 19-12 19-8 CMF EEPROM Array Address Fields .............................................................. 19-12 19-9 Program Interlock State Descriptions .............................................................. 19-21 19-10 Results of Programming Margin Read ...

Page 46

... Freescale Semiconductor, Inc. Table Number 22-1 JTAG Interface Pin Descriptions........................................................................ 22-3 22-2 Instruction Decoding .......................................................................................... 22-5 22-3 Boundary Scan Bit Definition ........................................................................... 22-10 A-1 SPR (Special Purpose Registers) ......................................................................... A-2 A-2 CMF (CDR MoneT Flash EEPROM) Flash Array ................................................. A-4 A-3 USIU (Unified System Interface Unit).................................................................... A-5 A-4 CMF (CDR MoneT Flash EEPROM) ...

Page 47

... Freescale Semiconductor, Inc. Table Number G-17 QSPI Timing..................................................................................................... G-53 G-18 GPIO Timing .................................................................................................... G-57 G-19 TPU3 Timing .................................................................................................... G-57 G-20 TouCAN Timing ............................................................................................... G-58 G-21 MCPSM Timing Characteristics ....................................................................... G-59 G-22 MPWMSM Timing Characteristics ................................................................... G-60 G-23 MMCSM Timing Characteristics ...................................................................... G-62 G-24 MDASM Timing Characteristics ....................................................................... G-65 G-25 MPIOSM Timing Characteristics ...

Page 48

... Freescale Semiconductor, Inc. Table Number MPC555 / MPC556 USER’S MANUAL For More Information On This Product, LIST OF TABLES Rev. 15 October 2000 Go to: www.freescale.com Page Number MOTOROLA xlviii ...

Page 49

... Freescale Semiconductor, Inc. This manual defines the functionality of the MPC555 / MPC556 for use by software and hardware developers. The MPC555 / MPC556 is based on the PowerPC proces- sor used in the Motorola MPC500 family of microcontrollers. For further information refer to the MPC500 Family RCPU Reference Manual, RCPURM/AD number) ...

Page 50

... Freescale Semiconductor, Inc certain contexts, such as a signal encoding, this indicates a don’t care. For example field is binary encoded 0bx001, the state of the first bit is a don’t care. Throughout this manual references refer to the nominal supply voltage of 3.3 volts. Nomenclature Logic level one is the voltage that corresponds to Boolean true (1) state ...

Page 51

... Freescale Semiconductor, Inc. The MPC555 / MPC556 is a member of Motorola’s MPC500 PowerPC controller family. The MPC555 / MPC556 offers the following features: • PowerPC core with floating-point unit • 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM • 448 Kbytes flash EEPROM with 5-V programming • ...

Page 52

... Freescale Semiconductor, Inc. Burst Interface RCPU 16 Kbytes SRAM QADC QADC TPU3 DPTRAM Figure 1-1 MPC555 / MPC556 Block Diagram 1.2 MPC555 / MPC556 Features Features of each module on the MPC555 / MPC556 are listed below. 1.2.1 RISC MCU Central Processing Unit (RCPU) • 32-bit PowerPC architecture (compliant with PowerPC Architecture Book 1) • ...

Page 53

... Freescale Semiconductor, Inc. — On-chip emulation (OnCE 1.2.2 Four-Bank Memory Controller • Works with SRAM, EPROM, flash EEPROM, and other peripherals • Byte write enables • 32-bit address decodes with bit masks • Memory transfer start (MTS): This pin is the transfer start signal to access a slave’ ...

Page 54

... Freescale Semiconductor, Inc. 1.2.7 General-Purpose I/O Support • Address (24) and data (32) pins can be used for general-purpose I/O in single- chip mode • 9 general-purpose I/O pins in MIOS1 unit • Many peripheral pins can be used for general-purpose I/O when not used for pri- mary function • ...

Page 55

... Freescale Semiconductor, Inc. 1.2.11 Two CAN 2.0B Controller Modules (TouCANs) Each TouCAN provides these features: • Full implementation of CAN protocol specification, version 2.0 A and B • Each module has 16 receive/transmit message buffers bytes data length • Global mask register for message buffers • ...

Page 56

... Freescale Semiconductor, Inc. 0x0000 0000. (Refer to Figure location allows the user to implement a multiple-chip system. 0x0000 0000 0x003F FFFF 0x0040 0000 0x007F FFFF 0x0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 0x013F FFFF 0x0140 0000 0x017F FFFF 0x0180 0000 0x01BF FFFF ...

Page 57

... Freescale Semiconductor, Inc. 0x00 0000 CMF Flash A 256 Kbytes 0x04 0000 CMF Flash B Kbytes 192 0x06 FFFF 0x07 0000 Reserved for Flash (2.6 Mbytes - 16 Kbytes) – BFFF 000 & ash 16 Kbytes 0x 2F FFFF 0x 30 0000 UIMB Interface & IMB3 Modules (32 Kbytes) ...

Page 58

... Freescale Semiconductor, Inc. / MPC555 MPC556 USER’S MANUAL For More Information On This Product, OVERVIEW Rev. 15 October 2000 Go to: www.freescale.com MOTOROLA 1-8 ...

Page 59

... Freescale Semiconductor, Inc. SIGNAL DESCRIPTIONS 2.1 Packaging and Pinout Descriptions Figure 2-1 gives the case configuration and packaging information for the MPC555 / MPC556. Figure 2-2 gives the MPC555 / MPC556 pinout data. overview of the pins on the MPC555 / MPC556. MPC555 / MPC556 USER’S MANUAL ...

Page 60

... Freescale Semiconductor, Inc. PIN 1 D INDEX 0 TOP VIEW (D1) 19X e 19X (E1 BOTTOM VIEW Figure 2-1 MPC555 / MPC556 Case Dimensions and Packaging / MPC555 MPC556 USER’S MANUAL For More Information On This Product, C 272X 0 SIDE VIEW 272X 0 0.15 M CASE 1135A–01 ISSUE B SIGNAL DESCRIPTIONS Rev ...

Page 61

... Freescale Semiconductor, Inc. Figure 2-2 MPC555 / MPC556 Pinout Data / MPC555 MPC556 USER’S MANUAL For More Information On This Product, SIGNAL DESCRIPTIONS Rev. 15 October 2000 Go to: www.freescale.com MOTOROLA 2-3 ...

Page 62

... Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA Functional Group 24 Address lines (16-Mbyte address space) 32-bit data bus External interrupts Bus control General purpose chip select ma- chine (multiplexed with development and debug support) Power-on reset and reset ...

Page 63

... Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group Clocks and PLL QSMCM MIOS General-Purpose I/O from MIOS TPU QADC A_AN[48:51]/PQB[4:7], B_AN[48:51]/PQB[4:7] A_AN[55:56]/PQA[3:4], B_AN[55:56]/PQA[3:4] A_AN[57:59]/PQA[5:7], B_AN[57:59]/PQA[5:7] TouCAN Flash EEPROM ...

Page 64

... Freescale Semiconductor, Inc. Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued) Functional Group High voltage Supply Programming Voltage NOTES: 1. “/” implies that the corresponding functions are multiplexed on the pin 2. All inputs are 5 V friendly. All 5 V outputs are slow slew rate except for SCI transmit pins. ...

Page 65

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table Pin Function Driver ADDR[8:31] ADDR[8:31]/ SGPIOA[8:31] SGPIOA[8:31] DATA[0:31] DATA[0:31] SGPIOD[0:31] SGPIOD[0:31] IRQ[0] IRQ[0]/ SGPIOC[0] SGPIOC[0] IRQ[1] IRQ[1]/RSV/ RSV SGPIOC[1] SGPIOC[1] IRQ[2] IRQ[2]/CR/ CR SGPIOC[2]/ MTS SGPIOC[2] MTS IRQ[3] IRQ[3]/KR, RETRY/ KR, RETRY SGPIOC[3] ...

Page 66

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table (Continued) Pin Function Driver BDIP BDIP TEA TEA RSTCONF RSTCONF/ 2 TEXP TEXP BI/STS STS CS[0:3] CS[0:3] WE[0:3]/BE[0:3] WE[0:3]/ BE[0:3]/AT[0:3] AT[0:3] 2 PORESET PORESET 2 HRESET HRESET ,2 SRESET SRESET SGPIOC[6] SGPIOC[6]/ FRZ/PTR FRZ PTR ...

Page 67

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table (Continued) Pin Function Driver TCK TCK/DSCK DSCK TDO TDO/DSDO DSDO TRST TRST 2 XTAL XTAL 2 EXTAL EXTAL XFC XFC CLKOUT CLKOUT 2 EXTCLK EXTCLK ENGCLK ENGCLK/ BUCLK BUCLK PCS0 TP/OD PCS0/ SS TP/OD SS/QGPIO[0] QGPIO[0] TP/OD ...

Page 68

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table (Continued) Pin Function Driver MPWM[0:3], MPWM[0:3], [16:19] [16:19] VF[0:2] VF[0:2]/ MPIO32B[0:2] MPIO32B[0:2] VFLS[0:1] VFLS[0:1]/ MPIO32B[3:4] MPIO32B[3:4] MPIO32B[5:15] MPIO32B[5:15] A_TPUCH[0:15] TPUCH[0:15] A_T2CLK T2CLK B_TPUCH[0:15] TPUCH[0:15] B_T2CLK T2CLK ETRIG[1:2] ETRIG[1:2] AN0 AN0/ ANW ANW/ PQB0 ...

Page 69

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table (Continued) Pin Function Driver AN[55:56] AN[55:56]/ PQA[3:4] PQA[3:4] AN[57:59] AN[57:59]/ PQA[5:7] PQA[5:7] AN0 AN0/ANW/ ANW PQB0 PQB0 AN1 ANX AN1/ANX/PQB1 PQB1 AN2 ANY AN2/ANY/PQB2 PQB2 AN3 ANZ AN3/ANZ/PQB3 PQB3 AN[48:51] AN[48:51]/ PQB[4:7] PQB[4:7] ...

Page 70

... Freescale Semiconductor, Inc. Table 2-2 Pin Functionality Table (Continued) Pin Function Driver EPEE EPEE VPP VPP VDDA VDDA VDDF VDDF VDDL VDDL VDDH VDDH VDDI VDDI VDDSYN VDDSYN VRH VRH VRL VRL VSSA VSSA VSSF VSSF VSSSYN VSSSYN 2 KAPWR KAPWR VDDSRAM ...

Page 71

... Freescale Semiconductor, Inc. SGPIO – This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.2 DATA[0:31]/SGPIOD[0:31] Pin Name: data_sgpiod[0:31] (32 pins) Data Bus – Provides the general purpose data path between the chip and all other devices. Although the data path is a maximum of 32 bits wide, it can be sized to sup- port 8-, 16-, or 32-bit transfers. DATA[0] is the MSB of the data bus. SGPIO – ...

Page 72

... Freescale Semiconductor, Inc. Interrupt Request – One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Kill Reservation – In case of a bus cycle initiated by a STWCX instruction issued by the CPU core to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. Retry – ...

Page 73

... Freescale Semiconductor, Inc. Transfer size – Indicates the size of the requested data transfer in the current bus cy- cle. 2.3.1.11 RD/WR Pin Name: rd_wr_b Read/Write – Indicates the direction of the data transfer for a transaction. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. ...

Page 74

... Freescale Semiconductor, Inc. Transfer Error Acknowledge – This signal indicates that a bus error occurred in the current transaction. The MCU asserts this signal when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. The assertion of TEA causes the termination of the current bus cycle, regardless of the state of TEA. An ex- ternal pull-up device is required to negate TEA quickly, before a second error is de- tected ...

Page 75

... Freescale Semiconductor, Inc. 2.3.1.21 WE[0:3]/BE[0:3]/AT[0:3] Pin Name: we_b_at[0:3](4 pins) Write Enable[0:3]/Byte Enable[0:3] – This output line is asserted when a write ac- cess to an external slave controlled by the GPCM in the memory controller is initiated by the chip. It can be optionally be asserted on all read and write accesses. See WEBS ...

Page 76

... Freescale Semiconductor, Inc. SGPIO – This function allows the pins to be used as general purpose inputs/outputs. Freeze – Indicates that the RCPU is in debug mode. Program Trace – Indicates an instruction fetch is taking place in order to allow pro- gram flow tracking. 2.3.1.26 SGPIOC[7]/IRQOUT/LWP[0] Pin Name: sgpioc7_irqout_b_lwp0 SGPIO – ...

Page 77

... Freescale Semiconductor, Inc. Bus Busy – Indicates that the master is using the bus. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. Visible Instruction Queue Flush Status – This output line together with VF0 and VF1 is output by the chip when a program instructions flow tracking is required by the user ...

Page 78

... Freescale Semiconductor, Inc. Test Data Out – This output is used for serial test instructions and test data for on- board test logic (JTAG). Development Serial Data Output – This output line is the data-out line of the debug port interface. See SECTION 21 DEVELOPMENT SUPPORT 2 ...

Page 79

... Freescale Semiconductor, Inc. VDDSYN – This is the power supply of the PLL circuitry. 2.3.1.42 VSSSYN Pin Name: vsssyn VSSSYN – This is the power supply of the PLL circuitry. 2.3.1.43 ENGCLK/BUCLK Pin Name: engclk_buclk ENGCLK – This is the engineering clock output. Drive strength can be configured to full strength, half strength or disabled ...

Page 80

... Freescale Semiconductor, Inc. 2.3.2.4 MOSI/QGPIO[5] Pin Name: mosi_qgpio5 Master-Out Slave-In (MOSI) – This bi-directional signal furnishes serial data output from the QSPI in master mode and serial data input to the QSPI in slave mode. QGPIO[5] – When this pin is not needed for a QSPI application it can be configured as a general purpose input/output ...

Page 81

... Freescale Semiconductor, Inc. 2.3.3 MIOS PADS 2.3.3.1 MDA[11], [13] Pin Name: mda11, mda13 (2 pins) Double Action – Each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. Clock Input – Each of these pins provide a clock input to the modulus counter sub- module ...

Page 82

... Freescale Semiconductor, Inc. Visible History Buffer Flush Status – These signals are output by the chip to allow program instruction flow tracking. They report the number of instructions flushed from the history buffer in the RCPU. See tails. MIOS GPIO – This function allows the pins to be used as general purpose inputs/out- puts ...

Page 83

... Freescale Semiconductor, Inc. Port (PQB0) – Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before it is sent internally to the QADC. 2.3.5.3 AN[1]/ANX/PQB[1]_[A:B] Pin Name: a_an1_anx_pqb1 (1 pin for first QADC), b_an1_anx_pqb1 (1 pin for sec- ond QADC) Analog Channel (AN1) – ...

Page 84

... Freescale Semiconductor, Inc. 2.3.5.7 AN[52:54]/MA[0:2]/PQA[0:2]_[A:B] Pin Name: a_an52_ma0_pqa0 – a_an54_ma2_pqa2 (3 pins for first QADC), b_an52_ma0_pqa0 – b_an54_ma2_pqa2 (3 pins for second QADC). Analog Input (AN[52:54]) – Input-only. The input is passed separate signal to the QADC. Multiplexed Address (MA[0:2]) – Output. Provides a three-bit multiplexed address output to the external multiplexer chip to allow selection of one of the eight inputs. Port (PQA[0:2]) – ...

Page 85

... Freescale Semiconductor, Inc. TouCAN Transmit Data 0 – This signal is the serial data output. 2.3.6.2 CNRX0_[A:B] Pin Name: a_cnrx0 (1 pin for first CAN), b_cnrx0 (1 pin for second CAN) TouCAN Receive Data – This signal furnishes serial input data. 2.3.7 CMF PADS 2.3.7.1 EPEE Pin Name: epee EPEE – ...

Page 86

... Freescale Semiconductor, Inc. 2.3.8.3 VDDI Pin Name: vddi VDDI – 3-V voltage supply input for internal logic. 2.3.8.4 VSSI Pin Name: vssi VSSI – Zero supply input for internal logic. In packaged devices, VSSI is not a sepa- rate input from VSS. 2.3.8.5 KAPWR Pin Name: kapwr Keep-Alive Power – ...

Page 87

... Freescale Semiconductor, Inc 3-V bus pins full drive (50-pF load 3-V bus pins reduced drive (25-pF load) * The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register (for the TPU, QADC, USIU (SGPIO), QSPI, TouCAN, QSCI, and MIOS pins). ...

Page 88

... Freescale Semiconductor, Inc. Table 2-3 PDMCR Bit Descriptions (Continued) Bit(s) Name The SPRDS bit is used to enable or disable the weak pull-up/pull-down devices in special 3-V only bus pads. Table 2-4 7 SPRDS this bit affects the pins see 0 = Enable pull-up/pull-down devices 1 = Disable pull-up/pull-down devices Follow TPU Pull-Up — ...

Page 89

... Freescale Semiconductor, Inc. 2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins Two signals are needed to enable or disable the pull-up/pull-down devices in the 3-V / 5-V multiplexed pads: • The PRDS signal • An encoded 3-V / 5-V select 2.4.6.1 PRDS Signal The PRDS signal is derived from the PRDS bit in the PDMCR ...

Page 90

... Freescale Semiconductor, Inc. 2.4.7 Special Pull Resistor Disable Control (SPRDS) For the pins that support debug and opcode-tracking functionality, the pull-up and pull- down resistors are controlled by the SPRDS signal, which is somewhat like the encod- ed 3-V / 5-V select. During reset this signal is used synchronously to enable the pull- up resistors in the pads ...

Page 91

... Freescale Semiconductor, Inc. Table 2-4 Pin Reset State (Continued) Pin Function IRQ[5] IRQ[5]/SGPIOC[5]/ SGPIOC[5] 3 MODCK[1] MODCK[1] IRQ[6:7] IRQ[6:7]/ 3 MODCK[2:3] MODCK[2:3] TSIZ[0:1] TSIZ[0:1] RD/WR RD/WR BURST BURST BDIP BDIP TEA TEA RSTCONF 3 RSTCONF/TEXP TEXP OE OE BI4 BI/STS STS CS[0:3] CS[0:3] WE[0:3]/BE[0:3] ...

Page 92

... Freescale Semiconductor, Inc. Table 2-4 Pin Reset State (Continued) Pin Function SGPIOC[7] SGPIOC[7/ IRQOUT IRQOUT/LWP[0] LWP[0] BG BG/ VF[0]/ VF[0] LWP[1] LWP[1] BR BR/ VF[1]/ VF[1] IWP[2] IWP[ BB/ VF[2]/ VF[2] IWP[3] IWP[3] IWP[0:1] IWP[0:1]/ VFLS[0:1] VFLS[0:1] TMS TMS TDI TDI/ DSDI DSDI TCK ...

Page 93

... Freescale Semiconductor, Inc. Table 2-4 Pin Reset State (Continued) Pin Function PCS0 PCS0/ SS/ SS QGPIO[0] QGPIO[0] PCS[1:3] PCS[1:3]/ QGPIO[1:3] QGPIO[1:3] MISO MISO/ QGPIO[4] QGPIO[4] MOSI MOSI/ QGPIO[5] QGPIO[5] SCK SCK/ QGPIO[6] QGPIO[6] TXD[1:2] TXD[1:2]/ QGPO[1:2] QGPO[1:2] RXD[1:2] RXD[1:2]/QGPI[1:2] QGPI[1:2] ECK ...

Page 94

... Freescale Semiconductor, Inc. Table 2-4 Pin Reset State (Continued) Pin Function AN3 A: AN3/ANZ/PQB3 ANZ PQB3 AN[48:51] A: AN[48:51]/ PQB[4:7] PQB[4:7] AN[52:54] A: AN[52:54]/ MA[0:2] MA[0:2]/PQA[0:2] PQA[0:2] AN[55:56] A: AN[55:56]]/ PQA[3:4] PQA[3:4] AN[57:59] A: AN[57:59]/ PQA[5:7] PQA[5:7] AN0 B: AN0/ANW/PQB0 ANW PQB0 AN1 B: AN1/ANX/PQB1 ANX PQB1 ...

Page 95

... Freescale Semiconductor, Inc. Table 2-4 Pin Reset State (Continued) Pin Function EPEE EPEE VPP VPP VDDF VDDF VSSF VSSF VDDL VDDL VDDH VDDH VDDI VDDSI VSSI VSSI 3 KAPWR KAPWR VDDSRAM VDDSRAM VDDSYN VDDSYN VSS VSS VSSSYN VSSSYN NOTES: 1. During reset, the output enable to the pad driver is negated and the PU3/PU5 is active. After reset is negated, the output enable is continuously enabled and the PU3 is disabled ...

Page 96

... Freescale Semiconductor, Inc. • Drive select – Selects the drive strength of the pad. For example, data pin drivers can be configured to drive a 25-pF load or a 50-pF load. • Synchronizer clock – Some pins have synchronizer logic to handle metastable signals at the input of a pin. For pads that have synchronizers and support syn- chronized or normal data input, the corresponding interface signals to the internal logic are “ ...

Page 97

... Freescale Semiconductor, Inc. Drive Sel Sprds Data Out Logic OE 2.5.2.2 Type B Interface (Clock Pad) The pad has a capability to select the buffer for the appropriate load ( pF). The OE input drives the totem pole output or three-states the output. Drive Sel Data Out Logic OE 2.5.3 Three-Volt Input Pad ...

Page 98

... Freescale Semiconductor, Inc. (no resistor), and one with a pull-down resistor. The SPRDS signal may disable the pull-up or pull-down resistor. 2.5.3.1 Type C Interface The type C interface has a 3-V input with a pull-up resistor. Data In Sprds 2.5.3.2 Type CH Interface Pad type CH has a 3-V input with hysteresis and a pull-up resistor. The hyst_sel signal selects the receiver with or without hysteresis ...

Page 99

... Freescale Semiconductor, Inc. 2.5.3.3 Type CNH Interface The CNH pad type has a 3-V input with hysteresis but no pull-up or pull-down device. Data In Figure 2-7 Type CNH Interface 2.5.3.4 Type D Interface This type of pad has a 3-V input and an internal pull-down resistor. Data In Sprds 2 ...

Page 100

... Freescale Semiconductor, Inc. 2.5.4.1 Type E Interface In this pad type the data interface to the internal logic has separate paths for input and output. This pad also has a open drain enable input. For totem pole driven outputs, the signal is connected to VSS to disable the open-drain drive. ...

Page 101

... Freescale Semiconductor, Inc. Drive Sel Sprds Data Out Logic OE Data In IE Figure 2-10 3-V Type EOH Interface 2.5.4.3 Type F Interface In this pad type the data interface to the internal logic has the same path for both input and output. The pull-up is inactive when the driver is enabled. ...

Page 102

... Freescale Semiconductor, Inc. Drive Sel Sprds Data IO Logic OE IE Figure 2-11 Type F Interface 2.5.4.4 Type G Interface In this pad type the data interface to the internal logic has the same path for both input and output. This pad type also has the SPRDS signal as an input to disable the resistor when the pad is a non-bus function ...

Page 103

... Freescale Semiconductor, Inc. Sprds Drive Sel Data Out Logic OE Data In IE Figure 2-12 Type G Interface 2.5.5 Five-Volt Input/Output Pad This pad type is for 5-V bi-directional pins. There is provision to pull the pin and logic to control when the pull-up is enabled. For a 5-V driver, the internal “Fast Mode” ...

Page 104

... Freescale Semiconductor, Inc. 3-V / 5-V Sel PRDS Drive Sel 5 V Data Out Logic 3 V Data Out OE SLRC Synch. Data In Synch. Clk Figure 2-13 Type H Interface 2.5.5.2 Type I Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. ...

Page 105

... Freescale Semiconductor, Inc. 3-V / 5-V Sel PRDS Data Out Logic OE Drive Sel SLRC Data In IE 2.5.5.3 Type IH Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal determines which driver gets selected. ...

Page 106

... Freescale Semiconductor, Inc. 3-V / 5-V Sel PRDS Data Out Logic OE Drive Sel SLRC Data In IE hyst_sel Figure 2-15 Type IH Interface 2.5.5.4 Type J Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal indicates which driver gets selected. The data inter- face to the internal logic has the same path for both input and output ...

Page 107

... Freescale Semiconductor, Inc. 3-V / 5-V Sel PRDS Data Logic OE Drive Sel SLRC IE Figure 2-16 Type J Interface 2.5.5.5 Type JD Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A “3-V / 5-V sel” interface signal indicates which driver gets selected. ...

Page 108

... Freescale Semiconductor, Inc. 3-V / 5-V Sel PRDS Data Logic OE Drive Sel SLRC IE Figure 2-17 Type JD Interface 2.5.6 Type K Interface (EPEE Pad) This pad has a pull-down device that is enabled at all times. The module checks to see that a transition to a new state on the pin is maintained for at least two clocks before the information is passed on internally to the sequencer implemented in the flash ...

Page 109

... Freescale Semiconductor, Inc. Data Synch. Clk Figure 2-18 EPEE Pad (Type K) 2.5.7 Analog Pads The 5-V analog pads interface to the QADC modules internally. They have separate analog and digital paths in the pad in order to implement the functionality that is mul- tiplexed on the pin. ...

Page 110

... Freescale Semiconductor, Inc. PRDS Analog In Dig. Out Data Direction Dig. In Input Enable Sync. Clk Figure 2-19 Type L Interface 2.5.7.2 Type M Interface (QADC Port B) This pad is used for interfacing to port B of the QADC. This is an input-only pad. The receiver has a synchronizer. The digital input is level-shifted from before it is sent internally to the QADC ...

Page 111

... Freescale Semiconductor, Inc. 2.5.7.3 Type N Interface (ETRIG) This is the pad for the ETRIG function of the QADC. The input signal is level-shifted before being sent to the QADC module. The pad also serves as an output pad in test mode. Input Enable Dig. In Sync. Clk Figure 2-21 Type N Interface 2 ...

Page 112

... Freescale Semiconductor, Inc. SLRC OD Enable PRDS Data Out Logic OE Normal Data In Synch. Data In Synch. Clk Figure 2-22 Type O Interface 2.5.8.2 Type P Interface (TPU and MIOS Pads) This is a 5-V, bi-directional pad that has a fast mode provision like the QSMCM pads. The input path is always synchronous. The receiver has hysteresis in order to mini- mize the effect of noise on the pins ...

Page 113

... Freescale Semiconductor, Inc. SLRC PRDS Data Out Logic OE Synch. Data In Synch. Clk Figure 2-23 Type P Interface 2.5.9 5V Input, 5V Output Pads These pads are 5-V only pads. 2.5.9.1 5V Output (Type Q) This pad is a 5-V output-only pad with slow and fast drive capability. The driver is con- figureable to be either push pull or open drain using the OD enable signal ...

Page 114

... Freescale Semiconductor, Inc. PRDS OD Enable Data Out Logic OE SLRC Figure 2-24 Type Q Interface 2.5.9.2 Type R Interface This is a 5-V input-only pad with a synchronous and asynchronous receiver. Both syn- chronous and asynchronous data are driven in from the internal module that interfaces to this pad. A pull-up device can be controlled using the PRDS signal. ...

Page 115

... Freescale Semiconductor, Inc. 2.5.9.3 5V Output for Clock Pad This interface is used for a 5-V clock pad output. The drive select signal selects the buffer for a 45- or 90-pF load. Drive Sel Data Out Logic OE Figure 2-26 Type S Interface 2.6 Pad Groups A pad group is a set of pins that exhibits similar functional characteristics. Within a group the individual pads may be of different types ...

Page 116

... Freescale Semiconductor, Inc. 2.7 Pin Names and Abbreviations The following table lists the recommended abbreviations for all the pins on the MPC555 / MPC556. The abbreviations can be used in applications for which the actual name is too long. For example, they can be used to on circuit boards to map the pin location on the boards ...

Page 117

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List DATA[0:31]/SGPIOD[0:31] IRQ[0]/SGPIOC[0] IRQ[1]/RSV/SGPIOC[1] IRQ[2]/CR/SGPIOC[2]/MTS IRQ[3]/KR, RETRY/SGPIOC[3] IRQ[4]/AT[2]/SGPIOC[4] IRQ[5]/SGPIOC[5]/MODCK[1] IRQ[6:7]/MODCK[2:3] TSIZ[0:1] / MPC555 MPC556 USER’S MANUAL For More Information On This Product, ...

Page 118

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List RD/ WR BURST BDIP TS TA TEA RSTCONF/TEXP OE BI/STS CS[0:3] WE[0:3]/BE[0:3]/AT[0:3] PORESET HRESET SRESET SGPIOC[6]/FRZ/PTR/ SGPIOC[7]/IRQOUT/LWP[0] BG/VF[0]/LWP[1] BR/VF[1]/IWP[2] BB/VF[2]/IWP[3] IWP[0:1]/VFLS[0:1] TMS TDI/DSDI TCK/DSCK ...

Page 119

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List PCS0/SS/QGPIO[0] PCS[1:3]/QGPIO[1:3] MISO/QGPIO[4] MOSI/QGPIO[5] SCK/QGPIO[6] TXD[1:2]/QGPO[1:2] RXD[1:2]/QGPI[1:2] ECK MDA[11:15] MDA[27:31] MPWM[0:3], [16:19] VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] / MPC555 MPC556 USER’S MANUAL For More Information On This Product, ...

Page 120

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List MPIO32B[5:15] A: TPUCH[0:15] A: T2CLK / MPC555 MPC556 USER’S MANUAL For More Information On This Product, Pin Name Abbreviation mpio32b5 mpio5 mpio32b6 mpio6 mpio32b7 mpio7 mpio32b8 mpio8 mpio32b9 mpio9 mpio32b10 mpio10 mpio32b11 ...

Page 121

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List B: TPUCH[0:15] B: T2CLK ETRIG[1:2] A: AN0/ANW/PQB0 A: AN1/ANX/PQB1 A: AN2/ANY/PQB2 A: AN3/ANZ/PQB3 A: AN[48:51]/PQB[4:7] A: AN[52:54]/MA[0:2]/PQA[0:2] A: AN[55:56]]/PQA[3:4] A: AN[57:59]/PQA[5:7] B: AN0/ANW/PQB0 B: AN1/ANX/PQB1 B: AN2/ANY/PQB2 B: AN3/ANZ/PQB3 / MPC555 MPC556 USER’S MANUAL For More Information On This Product, ...

Page 122

... Freescale Semiconductor, Inc. Table 2-6 Pin Names and Abbreviations (Continued) Pin List B: AN[48:51]/PQB[4:7] B: AN[52:54]/MA[0:2]/PQA[0:2] B: AN[55:56]/PQA[3:4] B: AN[57:59]/PQA[5:7] VRH VRL VDDA VSSA A: CNTX0 B: CNTX0 A: CNRX0 B: CNRX0 EPEE VPP VDDF VSSF VDDL VDDH VDDI KAPWR VDDSRAM VSS / MPC555 MPC556 USER’ ...

Page 123

... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT The PowerPC-based RISC processor (RCPU) used in the MPC500 family of micro- controllers integrates five independent execution units: an integer unit (IU), a load/ store unit (LSU), and a branch processing unit (BPU), floating-point unit (FPU) and in- teger multiplier divider (IMD). The use of simple instructions with rapid execution times yields high efficiency and throughput for MPC555 / MPC556-based systems ...

Page 124

... Freescale Semiconductor, Inc. 3.2 RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU. RCPU L-DATA L-ADDR INSTRUCTION SEQUENCER INSTRUCTION PRE-FETCH QUEUE I-DATA BRANCH PROCESSOR UNIT I-ADDR NEXT ADDRESS GENERATION Figure 3-1 RCPU Block Diagram / MPC555 MPC556 USER’S MANUAL For More Information On This Product, ...

Page 125

... Freescale Semiconductor, Inc. 3.3 Instruction Sequencer The instruction sequencer provides centralized control over data flow between execu- tion units and register files. The sequencer implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history so it can back the machine up in the event of an exception ...

Page 126

... Freescale Semiconductor, Inc. INSTRUCTION MEMORY SYSTEM INSTRUCTION ADDRESS GENERATOR CC UNIT EXECUTION UNITS AND REGISTERS FILES Figure 3-2 Sequencer Data Path 3.4 Independent Execution Units The PowerPC architecture supports independent floating-point, integer, load/store, and branch processing execution units, making it possible to implement advanced fea- tures such as look-ahead operations ...

Page 127

... Freescale Semiconductor, Inc. Table 3-1 RCPU Execution Units Unit Branch processing Includes the implementation of all branch instructions unit (BPU) Includes implementation of all load and store instructions, whether defined as part Load/store unit (LSU) of the integer processor or the floating-point processor Includes implementation of all integer instructions except load/store instructions. ...

Page 128

... Freescale Semiconductor, Inc. The IU also includes the integer exception register (XER) and the general-purpose register file. IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU– BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles to execute. IMUL– ...

Page 129

... Freescale Semiconductor, Inc. 3.5 Levels of the PowerPC Architecture The PowerPC architecture consists of three layers. Adherence to the PowerPC archi- tecture can be measured in terms of which of the following levels of the architecture are implemented: • PowerPC user instruction set architecture (UISA) — Defines the base user-level ...

Page 130

... Freescale Semiconductor, Inc. USER MODEL UISA FPR0 FPR1 FPR31 0 GPR0 Condition GPR1 Register CR 0 GPR31 31 0 Floating-Point Status and Control Register FPSCR 0 User-Level SPRs Integer Exception Register (XER) Link Register (LR) Count Register (CTR USER MODEL VEA Time Base Facility (for Reading) Time Base Lower – ...

Page 131

... Freescale Semiconductor, Inc. Table 3-2 Supervisor-Level SPRs SPR Number (Decimal 272 273 274 275 284 285 287 528 536 560 / MPC555 MPC556 USER’S MANUAL For More Information On This Product, Special-Purpose Register DAE/Source Instruction Service Register (DSISR) See 3.9.2 DAE/Source Instruction Service Register (DSISR) for bit descriptions ...

Page 132

... Freescale Semiconductor, Inc. Table 3-2 Supervisor-Level SPRs (Continued) SPR Number (Decimal) 568 784 785 786 787 792 793 794 795 816 817 818 819 824 825 826 827 1022 NOTES: 1. Implementation-specific SPR. Table 3-3 lists the MPC555 / MPC556 SPRs used for development support. ...

Page 133

... Freescale Semiconductor, Inc. Table 3-3 Development Support SPRs SPR Number (Decimal) 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 630 NOTES: 1. All development-support SPRs are implementation-specific. Where not otherwise noted, reserved fields in registers are ignored when written and return zero when read ...

Page 134

... Freescale Semiconductor, Inc. 3.7.1 General-Purpose Registers (GPRs) Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below. These registers are accessed as source and destination registers through operands in the instruction syntax. GPRs — General-Purpose Registers MSB 3.7.2 Floating-Point Registers (FPRs) The PowerPC architecture provides thirty-two 64-bit FPRs ...

Page 135

... Freescale Semiconductor, Inc. FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except for the floating-point enabled exception summary (FEX) and float- ing-point invalid operation exception summary (VX). Once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction. ...

Page 136

... Freescale Semiconductor, Inc. Table 3-5 FPSCR Bit Descriptions Bit(s) Name Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if that instruction causes any of the floating-point exception bits in the FPSCR to change from The mcrfs instruction implicitly clears FPSCR[FX] if the FPSCR field containing FPSCR[FX] is copied ...

Page 137

... Freescale Semiconductor, Inc. Table 3-5 FPSCR Bit Descriptions (Continued) Bit(s) Name Floating-point invalid operation exception for software request. This bit can be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft- 21 VXSOFT ware to cause an invalid operation condition for a condition that is not necessarily associated with the execution of a floating-point instruction ...

Page 138

... Freescale Semiconductor, Inc. CR — Condition Register MSB CR0 CR1 CR2 The CR fields can be set in the following ways: • Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from a GPR. • Specified fields of the CR can be moved from one CRx field to another with the mcrf instruction. • ...

Page 139

... Freescale Semiconductor, Inc. Table 3-8 Bit Descriptions for CR1 Field of CR CR1 Bit Floating-point exception (FX) — This is a copy of the final state of FPSCR[FX] at the completion of the in- 0 struction. Floating-point enabled exception (FEX) — This is a copy of the final state of FPSCR[FEX] at the completion 1 of the instruction ...

Page 140

... Freescale Semiconductor, Inc. The bit definitions for XER, shown in struction considered as a whole, not on intermediate results. For example, the result of the Subtract from Carrying (subfcx) instruction is specified as the sum of three val- ues. This instruction sets bits in the XER based on the entire operation, not on an in- termediate sum ...

Page 141

... Freescale Semiconductor, Inc. 3.7.7 Count Register (CTR) The count register (CTR 32-bit register for holding a loop count that can be dec- remented during execution of branch instructions that contain an appropriately coded BO field. If the value in CTR is 0 before being decremented –1 afterward. The count register provides the branch target address for the Branch Conditional to Count Register (bcctrx) instruction. CTR — ...

Page 142

... Freescale Semiconductor, Inc. 3.9 PowerPC OEA Register Set The PowerPC operating environment architecture (OEA) includes a number of SPRs and other registers that are accessible only by supervisor-level instructions. Some SPRs are RCPU-specific; some RCPU SPRs may not be implemented in other Pow- erPC processors, or may not be implemented in the same way. ...

Page 143

... Freescale Semiconductor, Inc. Table 3-12 Machine State Register Bit Descriptions Bit(s) Name 0:12 — Reserved Power management enable 13 POW 0 = Power management disabled (normal operation mode Power management enabled (reduced power mode) 14 — Reserved Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception ...

Page 144

... Freescale Semiconductor, Inc. Table 3-12 Machine State Register Bit Descriptions (Continued) Bit(s) Name 28 — Reserved Decompression On/Off DC RCPU Normal Operation 1 MPEN 1 = RCPU is running in Compressed mode Recoverable exception (for machine check and non-maskable breakpoint exceptions Machine state is not recoverable Machine state is recoverable. ...

Page 145

... Freescale Semiconductor, Inc. 3.9.4 Time Base Facility (TB) — OEA As described in 3.8 PowerPC VEA Register Set — Time provides a 64-bit incrementing counter. The VEA defines user-level, read-only access to the TB. Writing to the TB is reserved for supervisor-level applications such as oper- ating systems and bootstrap routines. The OEA defines supervisor-level, write access to the TB. TB — ...

Page 146

... Freescale Semiconductor, Inc. clock in the MPC555 / MPC556, refer to MPC555 / MPC556 Internal Clock ister (SCCR). The DEC does not run after power-up and must be enabled by setting the TBE bit in the TBSCR register, see register. A decrementer exception may be signaled to software prior to initialization. DEC — Decrementer Register ...

Page 147

... Freescale Semiconductor, Inc. SRR1 — Machine Status Save/Restore Register 1 MSB general, when an exception occurs, SRR1[0:15] are loaded with exception-specific information, and MSR[16:31] are placed into SRR1[16:31]. 3.9.8 General SPRs (SPRG0–SPRG3) SPRG0–SPRG3 are 32-bit registers provided for general operating system use, such as performing a fast-state save and for supporting multiprocessor implementations. SPRG0– ...

Page 148

... Freescale Semiconductor, Inc. Table 3-16 Processor Version Register Bit Descriptions Bit(s) Name A 16-bit number that identifies the version of the processor and of the PowerPC architec- 0:15 VERSION ture. MPC555 / MPC556 value is 0x0002. A 16-bit number that distinguishes between various releases of a particular version. The ...

Page 149

... Freescale Semiconductor, Inc. FPECR — Floating-Point Exception Cause Register MSB SIE RESET RESERVED RESET listing of FPECR bit descriptions is shown in Table 3-18 FPECR Bit Descriptions Bit(s) Name SIE mode control bit 0 SIE 0 = Disable SIE mode 1 = Enable SIE mode [1:27] — Reserved Source operand C denormalized status bit ...

Page 150

... Freescale Semiconductor, Inc. 3.10 Instruction Set All PowerPC instructions are encoded as single words (32 bits). Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly sim- plifies instruction pipelining. ...

Page 151

... Freescale Semiconductor, Inc. Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory con- tents must be loaded into a register, modified, and then written back to the target lo- cation with distinct instructions. PowerPC processors follow the program flow when they are in the normal execution state ...

Page 152

... Freescale Semiconductor, Inc. Table 3-19 Instruction Set Summary (Continued) Mnemonic crorc crxor divw (divw. divwo divwo.) divwu divwu. divwuo divwuo. eieio eqv (eqv.) extsb (extsb.) extsh (extsh.) fabs (fabs.) fadd (fadd.) fadds (fadds.) fcmpo fcmpu fctiw (fctiw.) fctiwz (fctiwz.) fdiv (fdiv.) fdivs (fdivs ...

Page 153

... Freescale Semiconductor, Inc. Table 3-19 Instruction Set Summary (Continued) Mnemonic lfdux lfdx lfs lfsu lfsux lfsx lha lhau lhaux lhax lhbrx lhz lhzu lhzux lhzx lmw lswi lswx lwarx lwbrx lwz lwzu lwzux lwzx mcrf mcrfs mcrxr mfcr mffs (mffs.) mfmsr ...

Page 154

... Freescale Semiconductor, Inc. Table 3-19 Instruction Set Summary (Continued) Mnemonic mulli mullw (mullw. mullwo mullwo.) nand (nand.) neg (neg. nego nego.) nor (nor.) or (or.) orc (orc.) ori oris rfi rlwimi (rlwimi.) rlwinm (rlwinm.) rlwnm (rlwnm.) sc slw (slw.) sraw (sraw.) srawi (srawi.) srw (srw ...

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... Freescale Semiconductor, Inc. Table 3-19 Instruction Set Summary (Continued) Mnemonic stwbrx stwcx. stwu stwux stwx subf (subf. subfo subfo.) subfc (subfc. subfco subfco.) subfe (subfe. subfeo subfeo.) subfic subfme (subfme. subfmeo subfmeo.) subfze (subfze. subfzeo subfzeo.) sync tw twi xor (xor.) xori xoris 3 ...

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... Freescale Semiconductor, Inc. For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is considered to wrap around from the maximum effective address to effective address 0. Effective address computations for both data and instruction accesses use 32-bit un- signed binary arithmetic ...

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... Freescale Semiconductor, Inc. debug port non-maskable interrupt or machine check exception occurs during the ser- vicing of a previous exception, the machine state information in SRR0 and SRR1 (and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of saving or restoring these registers. ...

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... Freescale Semiconductor, Inc. Table 3-21 Exception Vector Offset Table Vector Offset (Hexadecimal) 00000 00100 00200 00300 00400 00500 00600 00700 00800 00900 00A00 00B00 00C00 00D00 00E00 01000 01100 01200 01300 01400 01500–01BFF 01C00 01D00 01E00 01F00 Implementation-dependent non-maskable external breakpoint 3 ...

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... Freescale Semiconductor, Inc the execute stage, each execution unit that has an executable instruction ex- ecutes the instruction. (For some instructions, this occurs over multiple cycles the writeback stage, the execution unit writes the result to the destination reg- ister and reports to the history buffer that the instruction is completed. ...

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... Freescale Semiconductor, Inc. Table 3-22 Instruction Latency and Blockage Instruction Type Floating-point multiply-add Floating-point add or subtract Floating-point multiply Floating-point divide Integer multiply Integer divide Integer load/store NOTES: Section 7 Instruction Timing, 1. Refer to Manual (RCPURM/AD) 3.13 PowerPC User Instruction Set Architecture (UISA) 3.13.1 Computation Modes The core of the MPC555 / MPC556 is a 32-bit implementation of the PowerPC archi- tecture ...

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... Freescale Semiconductor, Inc. tation-dependent software emulation interrupt. Invalid and preferred instruction forms treatment by the MPC555 / MPC556 is described under the specific processor compli- ance sections. 3.13.4 Exceptions Invocation of the system software for any instruction-caused exception in the MPC555 / MPC556 is precise, regardless of the type and setting. ...

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... Freescale Semiconductor, Inc. • Fixed-point rotate and shift instructions • Move to/from system register instructions All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of the various instructions, refer to — Move To/From System Register Instructions. Move to/from invalid special registers in which spr0 = 1 yields invocation of the privilege instruction error in- terrupt handler if the processor is in problem state ...

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... Freescale Semiconductor, Inc. 3.13.10.1 Fixed-Point Load With Update and Store With Update Instructions For load with update and store with update instructions, where the EA is writ- ten into R0. For load with update instructions, where boundedly unde- fined. 3.13.10.2 Fixed-Point Load and Store Multiple Instructions For these types of instructions, EA must be a multiple of four ...

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... Freescale Semiconductor, Inc. The following check is done on the stored operand in order to determine whether denormalized single-precision operand and invoke the floating-point assist interrupt handler handler: Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete description of handling denormalized floating-point numbers. 3.13.10.8 Optional Instructions No optional instructions are supported ...

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... Freescale Semiconductor, Inc. 3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction When executing an eieio instruction, the load/store unit will wait until all previous ac- cesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction. 3.14.5 Timebase A description of the timebase register may be found in URATION AND PROTECTION TROL ...

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... Freescale Semiconductor, Inc. DBAT3U, DBAT3L • Added Registers — For a list of added special purpose registers, refer to 3-2, and Table 3-3. 3.15.3 Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlb- sync are not implemented by the MPC555 / MPC556. ...

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... Freescale Semiconductor, Inc. 3.15.4.2 Machine Check Interrupt A machine check interrupt indication is received from the U-bus as a possible re- sponse either to the address or data phase usually caused by one of the following conditions: • The accessed address does not exist • A data error is detected As defined in the OEA, machine check interrupts are enabled when MSR ...

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... Freescale Semiconductor, Inc. Register Name Data/Storage Interrupt Status Register (DSISR) Data Address Register (DAR) 3.15.4.4 Instruction Storage Interrupt An instruction storage interrupt is never generated by the hardware. The software may branch to this location as a result of an implementation-specific instruction storage pro- tection error interrupt. ...

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... Freescale Semiconductor, Inc. 3.15.4.9 Floating-Point Unavailable Interrupt The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core as defined in the OEA. 3.15.4.10 Trace Interrupt A trace interrupt occurs if MSR pleted or MSR = 1 and a branch is completed. Notice that the trace interrupt does BE not occur after an instruction that caused an interrupt (for instance, sc). A monitor/de- bugger software must change the vectors of other possible interrupt addresses to sin- gle-step such instructions ...

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... Freescale Semiconductor, Inc. Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) NOTES the current implementation bit 30 of the SRR1 is never cleared other then by loading zero value from MSR RI. 3.15.4.12 Implementation-Dependent Software Emulation Interrupt An implementation-dependent software emulation interrupt occurs in the following in- stances: • ...

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... Freescale Semiconductor, Inc. Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Execution resumes at offset 0x01000 from the base address indicated by MSR 3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt The implementation-specific instruction storage protection error interrupt occurs in the following cases: • ...

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... Freescale Semiconductor, Inc. Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Execution resumes at offset 0x01300 from the base address indicated by MSR 3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt The implementation-specific data storage protection error interrupt occurs in the fol- lowing case: • ...

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... Freescale Semiconductor, Inc. Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Data/Storage Interrupt Status Register (DSISR) Data Address Register (DAR) Execution resumes at offset 0x01400 from the base address indicated by MSR 3.15.4.15 Implementation-Specific Debug Interrupts Implementation-specific debug interrupts occur in the following cases: • ...

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... Freescale Semiconductor, Inc. Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) For L-bus breakpoint instances, these registers are set to: Register Name BAR DAR and DSISR Execution resumes at offset from the base address indicated by MSR • 0x01D00 – For instruction breakpoint match • ...

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... Freescale Semiconductor, Inc. • Multiple/string instructions • Unaligned load/store instructions In the last case, the store instruction can be partially completed if one of the accesses (except the first one) causes the data storage protection error. The implementation- specific data storage protection interrupt is taken in this case. For the update forms, the update register (RA) is not altered ...

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... Freescale Semiconductor, Inc. / MPC555 MPC556 USER’S MANUAL For More Information On This Product, CENTRAL PROCESSING UNIT Rev. 15 October 2000 Go to: www.freescale.com MOTOROLA 3-54 ...

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... Freescale Semiconductor, Inc. The burst buffer module consists of the burst buffer controller (BBC) and the instruc- tion memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order to take full advantage of the U-bus bandwidth ...

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... Freescale Semiconductor, Inc. RCPU InstructionAddress Bus Figure 4-1 Burst Buffer Block Diagram 4.2 Burst Buffer Features The BBC offers the following features: • Supports pipelined access to internal memory and burstable access to the exter- nal memory. • Supports the de-coupled interface with the RCPU instruction unit. ...

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... Freescale Semiconductor, Inc. — Minimal performance penalty due to change of program flow execution • Two operation modes are available: “Decompression ON” and “Decompression OFF”. Switch between compressed and non-compressed user application soft- ware parts is possible. The IMPU has the following features: • ...

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... Freescale Semiconductor, Inc. • Slight changes in the core and existing RISC development tools — compilers, simulators, manually coded libraries. • Compressed address space four Megabytes (4 Mbytes). • Branch displacement from its target: — Conditional branch displacement two Kbytes (2 Kbytes). — Unconditional branch displacement two Mbytes (2 Mbytes). ...

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... Freescale Semiconductor, Inc. Original Code Figure 4-2 Example of Compressed Code Each instruction is divided to four bytes, marked X1, X2, X3 and X4. For each such byte a separate (Huffman coding) vocabulary is generated, marked Tx1, Tx2, Tx3 and Tx4. Once compressed, each instruction yields four symbols (corresponding to the X1, X2, X3, and X4 input bytes) ...

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... Freescale Semiconductor, Inc. 4.3.4 Memory Organization In order to enhance performance, the logic is built to decode two halves of an instruc- tion in parallel. The memory is arranged to support this as two streams of compressed symbols: the left stream for the compressed symbols of X1 and X2 bytes, and the right stream for the compressed symbols of X3 and X4 bytes ...

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... Freescale Semiconductor, Inc. The compiler will set the left and right stream boundary at either bit 12 or bit 19. This will be determined by the most efficient placement of compressed instruction code. The boundary will be placed between bits 11 and 12 if bit 31 is equal to one. The boundary will be placed between bits 18 and 19 if bit 31 is equal to zero. The original right and left streams may span an adjacent base addresses before or after each oth- er ...

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... Freescale Semiconductor, Inc. 4.3.5 Compressed Code Address Format The format of the compressed code in memory requires special addressing. The Decompressor module is responsible for generating compressed code addresses. The compressed instruction stream may start on any of the 32 bits. Thus, five bits are needed to locate such instruction inside a memory word. The instruction address in “ ...

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... Freescale Semiconductor, Inc. Base Address x x+4 0 Left/Right = X (don’t care) ( Left and Right are at the base address), Same_Line = 0 Base Address x x+4 0 Left/Right = 1 (Right side is first at the base address), Same_Line = 1 Base Address x x+4 0 Left/Right = 0 (Left side is first at the base address), Same_Line = 1 Figure 4-8 Examples of Instruction Layout in Memory 4.3.6 Compressed Address Format – ...

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... Freescale Semiconductor, Inc. branch has nine bits. This will yield a conditional branch displacement limit of two Kbytes. When a change of flow occurs, the sequencer of the PPC core will issue the new ad- dress in compression mapped format. The address extractor unit of the BBC gener- ates the direct branch address format to internal memory. ...

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... Freescale Semiconductor, Inc. An instruction in memory which will serve as the target of a branch will have a label attached. The label provides the needed pointer to the other half of the branch target instruction. The label token will be skipped in normal sequential operation. The label has three parts. First, the label prefix character (which is skipped by the decompres- sor) ...

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... Freescale Semiconductor, Inc. compression purposes. The resulting uncompressed elf code (with compression hooks) will load and run like any other elf code. The software compression tool compresses the elf code (x.elf) and produces a com- pressed elf code (x.elf.sqz). The system sees the compressed elf code as regular elf formatted code for purposes of loading into hardware (when programming the flash) ...

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... Freescale Semiconductor, Inc. code compression, and is a result of the statistical study. binary decode tree for specific instructions BYPS_node Figure 4-12 Bounded Huffman Code Tree In Figure 4-12, instruction “a” would require two bits. The bypass node would require four bits. The bounded form of the Huffman code tree is limited in size for implemen- tation into hardware. The largest compressed instruction is 36 bits — ...

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... Freescale Semiconductor, Inc. Compressed Instructions Memory COF Word-Aligned Physical Address Compressed Instruction Code Figure 4-13 Code Decompression Process 4.3.10 Compression Environment Initialization At power on reset (POR) or with a hard reset, the default settings will be activated unless the configuration word inputs override these defaults. The compression mode configuration data to be programmed is supplied by the user software in the flash ...

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... Freescale Semiconductor, Inc. 4.4.1 Normal Operation During normal operation, the burst buffer module transfers fetch accesses from the CPU to the U-bus. When a new access is issued by the CPU transferred in parallel to both the IMPU and the BBC. The IMPU compares the address of the access to its region programming ...

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... Freescale Semiconductor, Inc. The BE bit defined in 4.6.4 BBC Module Configuration Register (BBCMCR) mines whether the BBC operates burst cycles or not. Burst requests are enabled only when the BE bit is set. The negated state of the BE bit is useful mainly when the RCPU core runs in serialized mode. (Refer to Register for the ICTRL register ...

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... Freescale Semiconductor, Inc. 4.5.1 Exception Table Relocation Operation When an exception is requested, the CPU initiates a fetch cycle that branches to the exception routine associated with the exception that caused the fetch. The exception addresses are fixed within the RCPU architecture and are 0x100 bytes apart from each other, starting at address 0x0000_0100 or 0xFFF0_0100, depending on the val the MSR[IP] bit ...

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... Freescale Semiconductor, Inc. Table 4-1 Exception Addresses Mapping by BBC Name of Exception Reserved System Reset Machine Check Data Storage Instruction Storage External Interrupt Alignment Program Floating Point unavailable Decrementer Reserved Reserved System Call Trace Floating Point Assist Implementation Dependant Software Emulation Implementation Dependant Storage ...

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... Freescale Semiconductor, Inc. Exception Pointer by RCPU 0 100 200 300 400 500 600 700 1F00 Figure 4-14 Exception Table Entries Mapping / MPC555 MPC556 USER’S MANUAL For More Information On This Product, Internal Memory Structure F8 Main code can start here BURST BUFFER Rev. 15 October 2000 Go to: www ...

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... Freescale Semiconductor, Inc. 4.6 Burst Buffer Programming Model The BBC and IMPU module configuration registers are MPC555 / MPC556 special- purpose registers (SPRs). They are programmed with the MPC555 / MPC556 mtspr/ mfspr instructions. All the registers can be accessed in supervisor mode only. The processor generates an exception internally if an attempt is made to access the registers from user mode ...

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... Freescale Semiconductor, Inc. 4.6.1 Region Base Address Registers MI_RBA[0:3] — Region Base Address Register MSB RESET RESET: Table 4-5 MI_RBA[0:3] Bit Descriptions Bit(s) Name 0:19 RA Region address. This field defines the base address (most significant 20 bits) for the region. 20:31 — ...

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... Freescale Semiconductor, Inc. Table 4-6 MI_RA[0:3] Registers Bits Description Bit(s) Name Region size. The region size is a power of two, determined as follows: 0000_0000_0000_0000_0000 — 4 Kbytes 0000_0000_0000_0000_0001 — 8 Kbytes 0000_0000_0000_0000_0011 — 16 Kbytes 0000_0000_0000_0000_0111 — 32 Kbytes 0000_0000_0000_0000_1111 — 64 Kbytes 0000_0000_0000_0001_1111 — 128 Kbytes 0000_0000_0000_0011_1111 — 256 Kbytes 0000_0000_0000_0111_1111 — ...

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... Freescale Semiconductor, Inc. 4.6.3 Global Region Attribute Register Description (MI_GRA) MI_GRA — Global Region Attribute Register MSB ENR0 ENR1 ENR2 ENR3 RESET RESERVED PP RESET NOTES: 1. Available only on the MPC556. Table 4-7 MI_GRA Bit Descriptions Bit(s) Name Enable region 0 of IMPU 0 ENR0 ...

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... Freescale Semiconductor, Inc. 4.6.4 BBC Module Configuration Register (BBCMCR) BBCMCR — BBC Module Configuration Register MSB RESET RESERVED BE ETRE OERC RE- SET ID[19] NOTES: 1. Reset value is taken from the indicated bit of the reset configuration word. 2. Available only on the MPC556. Table 4-8 BBCMCR Bit Descriptions ...