MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 602

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

16.7 Programmer’s Model
MPC555
USER’S MANUAL
Table 16-10
register name represents “A” or “B” for the TouCAN_A or TouCAN_B module, respec-
tively. Refer to
in the MPC555 / MPC556 address map.
The column labeled “Access” indicates the privilege level at which the CPU must be
operating to access the register. A designation of “S” indicates that supervisor mode
is required. A designation of “S/U” indicates that the register can be programmed for
either supervisor mode access or unrestricted access.
The address space for each TouCAN module is split, with 128 bytes starting at the
base address, and an extra 256 bytes starting at the base address +128. The upper
256 are fully used for the message buffer structures. Of the lower 128 bytes, some are
not used. Registers with bits marked as “reserved” should always be written as logic 0.
Typically, the TouCAN control registers are programmed during system initialization,
before the TouCAN becomes synchronized with the CAN bus. The configuration reg-
isters can be changed after synchronization by halting the TouCAN module. This is
done by setting the HALT bit in the TouCAN module configuration register (CANMCR).
The TouCAN responds by asserting the CANMCR NOTRDY bit. Additionally, the con-
trol registers can be modified while the MCU is in background debug mode.
ILBS [1:0]
IMB3 CLOCK
IMB3 IRQ [7:0]
/
MPC556
The TouCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provid-
ed if the programming does not meet CAN protocol requirements.
shows the TouCAN address map. The lowercase “x” appended to each
1.3 MPC555 / MPC556 Address Map
Figure 16-5 Interrupt levels on IRQ with ILBS
Freescale Semiconductor, Inc.
00
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
01
IRQ
7:0
Go to: www.freescale.com
Rev. 15 October 2000
10
IRQ
15:8
NOTE
23:16
11
IRQ
31:24
00
IRQ
to locate each TouCAN module
01
IRQ
7:0
10
11
MOTOROLA
16-20