MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 664

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.2.2.1 Read Page Buffers
MPC555
USER’S MANUAL
0
Bit(s)
10:13
14:16
17:23
24:29
30:31
0:6
7:9
Each CMF array has two 32-byte read page buffers. The fully independent buffers are
located in two separate read sections of the array. Each page buffer status and ad-
dress are monitored in the BIU. The status of the read page buffers is made invalid by
any of the following operations:
Each access to the CMF EEPROM array determines whether the requested location
is within the current pages. If the requested location is not within the read page buffers,
the correct read page buffer is made invalid, and a new page of information is fetched
from the array. The page buffer address is updated and status is made valid. If the re-
quested location is within one of the current page buffers or has been fetched from the
array, the selected bytes are transferred to the U-bus, completing the access. CMF
EEPROM array accesses that make the page buffer(s) invalid (off-page reads) require
two system clocks. CMF EEPROM array accesses that do not make the page buffer(s)
1
2
0000000
• Reset
• Programming write
• Erase interlock write
• Setting EHV
• Clearing SES
• Setting or clearing SIE
Column Address
Array Hardware
/
Block Address
USIU Internal
Row Address
Byte Address
3
MPC556
Mapping
Mapping
4
Field
—
5
6
Table 19-8 CMF EEPROM Array Address Fields
7
Mapping
Internal
The seven high-order address bits of a CMF EEPROM array access (or any MPC555 /
MPC556 internal access) must equal zero.
These bits (programmed in the USIU internal memory map register) specify one of eight
locations for the MPC555 / MPC556 internal memory map.
These bits determine the location of each array within the MPC555 / MPC556 internal
memory map. Values are as follows:
Flash module A = 0000
Flash Module B = 0001
These three bits specify one of eight 32-Kbyte blocks within CMF Module A (000 to 111),
or one of six 32-Kbyte blocks within CMF Module B (000 to 101)
These seven bits select one of 128 rows within the 32-Kbyte block.
These six bits select one of 64 (word-length) columns within the row. Note also the follow-
ing:
ADDR[24:26] select a 32-byte read page.
ADDR[27:29] represent the read page word address.
ADDR[24:25] select a 64-byte program page.
ADDR[26:29] represent the program page word address.
Bits 30:31 select a byte within the column.
USIU
8
Freescale Semiconductor, Inc.
Table 19-7 EEPROM Array Addressing
For More Information On This Product,
9
1
0
Hardware
Mapping
CDR MoneT FLASH EEPROM
1
1
Array
Go to: www.freescale.com
1
2
Rev. 15 October 2000
1
3
1
4
Address
Block
1
5
1
6
1
7
Description
1
8
1
9
Address
Row
2
0
2
1
2
2
2
3
2
4
2
5
Address
Column
2
6
2
7
MOTOROLA
2
8
2
9
19-12
3
0
Byte
Addr
3
1