MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 141

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

CTR — Count Register
MSB
3.7.7 Count Register (CTR)
3.8 PowerPC VEA Register Set — Time Base
TB — Time Base (Read Only)
MPC555
USER’S MANUAL
0
32-63
0
0-31
Bits
The count register (CTR) is a 32-bit register for holding a loop count that can be dec-
remented during execution of branch instructions that contain an appropriately coded
BO field. If the value in CTR is 0 before being decremented, it is –1 afterward. The
count register provides the branch target address for the Branch Conditional to Count
Register (bcctrx) instruction.
The PowerPC virtual environment architecture (VEA) defines registers in addition to
those in the UISA register set. The PowerPC VEA register set can be accessed by all
software with either user- or supervisor-level privileges.
The PowerPC VEA includes the time base facility (TB), a 64-bit structure that contains
a 64-bit unsigned integer that is incremented periodically. The frequency at which the
counter is updated is implementation-dependent. For details on the time base clock in
the MPC555 / MPC556, refer to
/ MPC556 Internal Clock
CR).
The TB consists of two 32-bit registers: time base upper (TBU) and time base lower
(TBL). In the context of the VEA, user-level applications are permitted read-only ac-
cess to the TB. The OEA defines supervisor-level access to the TB for writing values
to the TB. Different SPR encodings are provided for reading and writing the time base.
In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the
entire 64-bit time base in a single instruction. The mftb simplified mnemonic copies
the lower half of the time base register (TBL) to a GPR, and the mftbu simplified mne-
monic copies the upper half of the time base (TBU) to a GPR.
1
2
Name
/
TBU
TBL
3
MPC556
4
Time Base (Upper) — The high-order 32 bits of the time base
Time Base (Lower) — The low-order 32 bits of the time base
5
Table 3-11 Time Base Field Definitions (Read Only)
6
7
TBU
8
Freescale Semiconductor, Inc.
For More Information On This Product,
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Signals, and
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
6.7 MPC555 / MPC556 Time Base
RESET: UNCHANGED
RESET: UNCHANGED
Loop Count
31 32
8.12.1 System Clock Control Register (SC-
Description
TBL
(TB),
SPR 268, 269
8.6 MPC555
MOTOROLA
SPR 9
3-19
63
LSB
31