MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 376

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.7 Memory Controller External Master Support
MPC555
USER’S MANUAL
The memory controller in the MPC555 / MPC556 supports accesses initiated by both
internal and external bus masters to external memories. If the address of any master
is mapped within the internal MPC555 / MPC556 address space, the access will be
directed to the internal device, and will be ignored by the memory controller. If the ad-
dress is not mapped internally, but rather mapped to one of the memory contoller re-
gions, the memory controller will provide the appropriate chip select and strobes as
programmed in the corresponding region (see
Register
The MPC555 / MPC556 supports only synchronous external bus masters. This means
that the external master works with CLKOUT and implements the MPC555 / MPC556
bus protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals
must be stable from the rising edge of CLKOUT during which TS is sampled, until the
last TA acknowledges the transfer. Since the external master works synchronously
with the MPC555 / MPC556, only setup and hold times around the rising edge of CLK-
OUT are important. Once the TS is detected/asserted, the memory controller com-
pares the address with each one of its defined valid banks to find a possible match.
But, since the external address space is shorter than the internal space, the actual ad-
dess that is used for comparing against the memory controller regions is in the format
of: {00000000, bits 8:16 of the external address}. In the case where a match is found,
the controls to the memory devices are generated and the transfer acknowledge indi-
cation (TA) is supplied to the master.
Since it takes two clocks for the external address to be recognized and handled by the
memory controller, the TS which is generated by the external master is ahead of the
corresponding CS and strobes which are asserted by the memory controller. This 2-
clock delay might cause problems in some synchronous memories. To overcome this,
the memory controller generates the MTS (memory transfer start) strobe which can be
used in the slave’s memory instead of the external master’s TS signal. As seen in
ure
troller so that the external memory can latch the external master’s address correctly.
To activate this feature, the MTSC bit must be set in the SIUMCR register. Refer to
6.13.1.1 SIU Module Configuration Register
When the external master accesses the internal flash when it is disabled, then the ac-
cess is terminated with transfer error acknowledge (TEA pin) asserted, and the mem-
ory controller does not support this access in any way.
When the memory controller serves an external master, the BDIP pin becomes an in-
put pin. This pin is watched by the memory controller to detect when the burst is ter-
minated.
10-18, the MTS strobe is synchronized to the assertion of CS by the memory con-
/
MPC556
(EMCR).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
for more information.
6.13.1.3 External Master Control
MOTOROLA
10-24
Fig-