MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 701

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.2.3 Sequential Instructions Marked as Indirect Branch
21.2.4 The External Hardware
21.2.4.1 Synchronizing the Trace Window to the CPU Internal Events
MPC555
USER’S MANUAL
cases the first instruction fetch after debug mode is marked with the program trace cy-
cle attribute and therefore is visible externally.
There are cases when non-branch (sequential) instructions may effect the machine in
a manner similar to indirect branch instructions. These instructions include rfi, mtmsr,
isync and mtspr to CMPA-F, ICTRL, ECR and DER.
These instructions are marked by the CPU as indirect branch instructions (VF = 101)
and the following instruction address is marked with the same program trace cycle at-
tribute as if it were an indirect branch target. Therefore, when one of these special in-
structions is detected in the CPU, the address of the following instruction is visible
externally. In this way the reconstructing software is able to evaluate correctly the ef-
fect of these instructions.
When program trace is needed, the external hardware needs to sample the status pins
(VF and VFLS) each clock cycle and the address of all cycles marked with the program
trace cycle attribute.
Program trace can be used in various ways. Below are two examples of how program
trace can be used:
The assertion/negation of VSYNC is done using the serial interface implemented in the
development port. In order to synchronize the assertion/negation of VSYNC to an in-
• Back trace — Back trace is useful when a record of the program trace before
• Window trace — Window trace is useful when a record of the program trace be-
/
some event occurred is needed. An example of such an event is some system
failure.
In case back trace is needed the external hardware should start sampling the sta-
tus pins (VF and VFLS) and the address of all cycles marked with the program
trace cycle attribute immediately when reset is negated. If show cycles is pro-
grammed out of reset to show all, all cycles marked with program trace cycle at-
tribute are visible on the external bus. VSYNC should be asserted sometime after
reset and negated when the programmed event occurs. If no show is pro-
grammed for show cycles, make sure VSYNC is asserted before the Instruction
show cycles programming is changed from show all.
Note that in case the timing of the programmed event is unknown it is possible to
use cyclic buffers.
After VSYNC is negated the trace buffer will contain the program flow trace of the
program executed before the programmed event occurred.
tween two events is needed. In case window trace is needed the VSYNC pin
should be asserted between these two events.
After the VSYNC pin is negated the trace buffer will contain information describing
the program trace of the program executed between the two events.
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
21-5