MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 278

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.8.3.4 Exiting from Power-Down Mode
8.8.3.5 Low-Power Modes Flow
MPC555
USER’S MANUAL
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500
PLL input frequency clocks. In one-to-one mode the wake-up time may be up to 100
PLL input frequency clocks. For a PLL input frequency of 4 MHz, the wake-up time is
less than 125 µs.
Exit from power-down mode is accomplished through hard reset. External logic should
assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted.
The TEXPS bit is set by an enabled RTC, PIT, time base, or decrementer interrupt.
The hard reset should be asserted for no longer than the time it takes for the power
supply to wake-up in addition to the PLL lock time. When the TEXPS bit is cleared (and
the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be
asserted, and causes an exit from power-down low-power mode. Refer to
Alive Power
Figure 8-9
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
/
MPC556
shows the flow among the different power modes.
for more information.
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
Rev. 15 October 2000
8.9.3 Keep
MOTOROLA
8-18