MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 683

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.7.8 Controlling the Program/Erase Voltage
19.8 Censored and Non-Censored Accesses
19.8.1 Uncensored Mode
19.8.2 Censored Mode
MPC555
USER’S MANUAL
The external program or erase enable pin (EPEE) and EHV are used to control the ap-
plication of the program or erase voltage to the CMF EEPROM module. High voltage
operations to the CMF EEPROM array, special MoneT shadow locations or FLASH
NVM registers can occur only if EHV = 1 and EPEE = 1.
Only after the correct hardware and software interlocks have been applied to the CMF
EEPROM can EHV be set. Once EHV is set SES cannot be changed and attempts to
read the array will not be acknowledged.
The default reset state of EHV disables program or erase pulses (EHV = 0). A master
reset while EHV = 1 terminates the high voltage operation, and CMF generates the re-
quired sequence to disable the high voltage without damage to the high voltage cir-
cuits. A soft reset or disabling the internal memory map clears EHV, terminating the
high voltage pulse.
The MPC555 / MPC556 always operates in one of two modes: censored or uncen-
sored.
Uncensored mode provides no censorship. In uncensored mode the FIC, ACCESS,
and CENSOR[0:1] bits are irrelevant. The MPC555 / MPC556 operates in uncensored
mode unless a specific event occurs to place the device in censored mode.
The MPC555 / MPC556 enters censored mode in response to any of the following
events:
The CMF EEPROM censorship mechanism provides several censorship levels. Four
bits in CMFMCR are used to configure the CMF censorship level. These bits are listed
in
In censored mode, the ACCESS and CENSOR bits work together according to
19-15.
Table
• Booting from external memory
• Any CMF array access from an external master
• Entering background debug mode.
/
ACCESS
FIC
CENSOR[0:1]
MPC556
19-14.
Overrides CENSOR[0:1] to force information censorship if ACCESS = 0
Determine the censorship level of the CMF
Enables a CMF EEPROM to bypass the censorship
Freescale Semiconductor, Inc.
Table 19-14 Censorship Control Bits
For More Information On This Product,
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
Table
19-31