MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 761

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

22.8 Non-IEEE 1149.1-1990 Operation
22.9 Boundary Scan Register
MPC555
USER’S MANUAL
In non-IEEE 1149.1-1990 operation, the IEEE 1149.1-1990 test logic must be kept
transparent to the system logic by forcing and holding the TAP controller into the test-
logic-reset controller state. There are two methods of forcing and holding the control-
ler to this state. The first is to assert the TRST signal, forcing the TAP into the test-
logic-reset controller state. The second is to provide at least five TCK pulses with
TMS held high.
The best approach is to connect a pull down resistor to TRST, or to connect it to
PORESET with a resistor. If bounday scan is required, the JTAG controller should
drive TRST to the negated state (“1” value) following PORESET.
The MPC555 / MPC556 scan chain implementation has a 346-bit boundary scan reg-
ister. This register contains bits for all device signal and clock pins and associated con-
trol signals. The XTAL, EXTAL and XFC pins are associated with analog signals and
are not included in the boundary scan register.
An IEEE-1149.1 compliant boundary scan register has been included on the MPC555
/ MPC556. This 346-bit boundary scan register can be connected between TDI and
TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. This register is
used for capturing signal pin data on the input pins, forcing fixed values on the output
signal pins, and selecting the direction and drive characteristics (a logic value or high
impedance) of the bidirectional and three-state signal pins.
ure 22-8
2. The TCK input is not blocked in low-power stop mode. To consume minimal
3. The TMS, TDI and TRST pins include on-chip pullup resistors. In low-power
/
MPC556
power, the TCK input should be externally connected to VDD or ground, al-
though TCK pin is internally connected to ground.
stop mode, these three pins should remain either unconnected or connected to
VDD to achieve minimal power consumption.
depict the various cell types.
For proper reset of the scan chain test logic, the best approach is to
assert TRST at power on reset (PORESET).
Freescale Semiconductor, Inc.
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
Figure 22-5
through
MOTOROLA
Fig-
22-7