MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 293

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
22:23
15
16
17
18
19
20
21
24
25
/
MPC556
TEXPS
LOLRE
SPLSS
TMIST
Name
CSRC
SPLS
LPM
CSR
—
—
Table 8-10 PLPRCR Bit Descriptions (Continued)
System PLL lock status bit
0 = SPLL is currently not locked
1 = SPLL is currently locked
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until soft-
ware clears it by writing a one to it. A write of zero has no effect on this bit. The bit is cleared
at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF change
and entering deep-sleep or power-down mode). The SPLSS bit is not affected by hard reset.
0 = SPLL has remained in lock
1 = SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in deep-
sleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
• The PIT is expired
• The real-time clock alarm is set
• The time base clock alarm is set
• The decrementer exception occurs
The bit remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. TEXPS is set by power-on or hard reset.
0 = TEXP is negated in deep-sleep mode
1 = TEXP pin remains asserted always
Reserved
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 = No timer expired event was detected
1 = A timer expire event was detected
Reserved
Clock source. This bit is cleared at hard reset.
0 = General system clock is determined by the DFNH value
1 = General system clock is determined by the DFNL value
Low-power mode select. These bits are encoded to provide one normal operating mode and
four low-power modes. In normal and doze modes, the system can be in high state (frequen-
cy determined by the DFNH bits) or low state (frequency defined by the DFNL bits). The LPM
field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the PLPRCR
Refer to
Checkstop reset enable. If this bit is set, then an automatic reset is generated when the
RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset.
If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon
receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part en-
ters debug mode upon entering checkstop mode. In this case, the RCPU will not assert the
checkstop signal to the reset circuitry. This bit is writable once after soft reset.
0 = No reset will occur when checkstop is asserted
1 = Reset will occur when checkstop is asserted
Loss of lock reset enable
0 = Loss of lock does not cause HRESET assertion
1 = Loss of lock causes HRESET assertion
Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See
8.12.3 Change of Lock Interrupt Register
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 8-4
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
and
Rev. 15 October 2000
Table
8-5.
Description
(COLIR).
MOTOROLA
8-33