MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 189

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

4.3.9 Decompression
MPC555
USER’S MANUAL
code compression, and is a result of the statistical study.
binary decode tree for specific instructions.
In
four bits. The bounded form of the Huffman code tree is limited in size for implemen-
tation into hardware. The largest compressed instruction is 36 bits — four bits for the
bypass mode plus the normal uncompressed 32-bit instruction.
1.
COF = Change of Flow
Figure
• The instruction code is stored in the memory in the compressed form
• The decode vocabulary is stored in the burst buffer controller (BBC).
• The decompression is done on-line by the dedicated decompressor unit in the
• Decompression flow: (See
BYPS_node
/
BBC.
— RCPU provides a “bit aligned COF
— ICDU:
MPC556
• Converts COF address to “word aligned physical address” to access the
• Fetches the compressed instruction code data from the memory, decom-
• When instructions are running without a COF, the next instruction is pre-
memory
presses it and delivers “non-compressed instruction code” together with
the bit aligned “next instruction address” to the RCPU, that uses it for sub-
routine and exceptions handling.
fetched and decoded in the current cycle. This eliminates any delays from
code compression during regular sequential (non-COF) operation.
4-12, instruction “a” would require two bits. The bypass node would require
Figure 4-12 Bounded Huffman Code Tree
Freescale Semiconductor, Inc.
b
For More Information On This Product,
e
Go to: www.freescale.com
d
Rev. 15 October 2000
a
Figure
BURST BUFFER
c
h
4-11)
1
g
address” to the BBC.
f
An “a” instruction half
requires less bits
than an “h” instruction
half.
A bypass instruction
requires four bits.
Figure 4-12
= another bit
= Instruction location
illustrates the
MOTOROLA
4-13