MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 41

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor, Inc.
Page
Table
Number
Number
9-3 Data Bus Contents for Write Cycles .................................................................... 9-30
9-4 Priority Between Internal and External Masters over External Bus ..................... 9-34
9-5 Burst Length and Order ....................................................................................... 9-36
9-6 BURST/TSIZE Encoding ..................................................................................... 9-37
9-7 Address Type Pins............................................................................................... 9-37
9-8 Address Types Definition..................................................................................... 9-38
9-9 Termination Signals Protocol............................................................................... 9-47
10-1 Timing Attributes Summary ............................................................................... 10-6
10-2 Programming Rules for Strobes Timing........................................................... 10-19
10-3 Boot Bank Fields Values After Hard Reset...................................................... 10-20
10-4 Write Enable/Byte Enable Signals Function .................................................... 10-21
10-5 Memory Controller Address Map ..................................................................... 10-27
10-6 MSTAT Bit Descriptions.................................................................................. 10-28
10-7 BR0 – BR3 Bit Descriptions............................................................................ 10-29
10-8 OR0 – OR3 Bit Descriptions ........................................................................... 10-30
10-9 DMBR Bit Descriptions ................................................................................... 10-32
10-10 DMOR Bit Descriptions.................................................................................. 10-33
11-1 DMPU Registers ................................................................................................ 11-6
11-2 Reservation Snoop Support............................................................................... 11-9
11-3 L2U_MCR LSHOW Modes ................................................................................ 11-9
11-4 L2U Show Cycle Support Chart....................................................................... 11-12
11-5 L2U (PPC) Register Decode............................................................................ 11-12
11-6 Hex Address For SPR Cycles.......................................................................... 11-13
11-7 L2U_MCR Bit Descriptions ............................................................................. 11-14
11-8 L2U_RBAx Bit Descriptions ............................................................................ 11-14
11-9 L2U_RAx Bit Descriptions .............................................................................. 11-15
11-10 L2U_GRA Bit Descriptions ........................................................................... 11-16
12-1 STOP and HSPEED Bit Functionality................................................................ 12-2
12-2 Bus Cycles and System Clock Cycles ............................................................... 12-3
12-3 ILBS Signal functionality .................................................................................... 12-5
12-4 IRQMUX Functionality ....................................................................................... 12-5
12-5 UIMB Interface Register Map ............................................................................ 12-7
12-6 UMCR Bit Descriptions ..................................................................................... 12-8
12-7 UIPEND Bit Descriptions ................................................................................... 12-9
13-1 Multiplexed Analog Input Channels ................................................................... 13-5
13-2 Analog Input Channels .................................................................................... 13-11
13-3 Queue 1 Priority Assertion............................................................................... 13-15
13-4 QADC64 Clock Programmability ..................................................................... 13-28
13-5 QADC64 Status Flags and Interrupt Sources.................................................. 13-30
13-6 QADC64 Address Map .................................................................................... 13-32
13-7 QADC64MCR Bit Descriptions ....................................................................... 13-33
13-8 QADC64INT Bit Descriptions.......................................................................... 13-34
MPC555 / MPC556
LIST OF TABLES
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
xli
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