M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 95

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
[ Selectable src ]
[ Flag Change ]
v
[ Function ]
[ Description Example ]
DIVU
[ Syntax ]
[ Operation ]
J
Chapter 3
*1 When (.B) and (.W) are specified for the size specifier (.size), indirect instruction addressing [src] can
Conditions
Change
1 .
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16/#IMM32
9
Flag
DIVU.size
• When the size specifier (.size) is (.L)
• When the size specifier (.size) is (.W)
• When the size specifier (.size) is (.B)
0 .
O :
B
DIVU.B
DIVU.B
DIVU.W
DIVU.W
DIVU.L
0
be used in all addressing except R0L/R0/-, R0H/R2/-, R1L/R1/-, R1/-, R1H/R3/-, and #IMM. When
(.size) is (.L), indirect instruction addressing [src] cannot be used.
0
• When (.B) is specified for the size specifier (.size), this instruction divides R0 by unsigned
• When (.W) is specified for the size specifier (.size), this instruction divides R2R0 by unsigned
• When (.L) is specified for the size specifier (.size), this instruction divides R2R0 by unsigned
3
1
2
stores the quotient in R0L and the remainder in R0H. When
low-order bits of the address register are used as data to be operated on. The O flag is set when the
operation resulted in the quotient exceeding 8 bits or the divider is 0. R0L and R0H is undefined.
stores the quotient in R0 and the remainder in R2. When
bits of the address register are used as data to be operated on. The O flag is set when the operation
resulted in the quotient exceeding 16 bits or the divider is 0. R0 and R2 is undefined.
stores the quotient in R2R0. The remainder is not operated. When
zero-extended to be treated as 32-bit data for the operation. The O flag is set when the divider is 0.
R2R0 is undefined.
9
0
U
0 -
0
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W), 8 bits (.B) or the
divider is 0; otherwise cleared.
6
1
0 .
0
0
5
I
3 .
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
Functions
1
A0
#4
R0
[[A0]]
R3R1
src
O
p
a
g
e
B
src*
77
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
1
f o
Z
3
3
5
D
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
DIVide Unsigned
B , W , L
Unsigned divide
R2R0 (quotient)
R0 (quotient), R2 (remainder)
R0L (quotient), R0H (remainder)
;A0's 8 low-order bits is the divider.
;The remainder is not operated.
src
[ Instruction Code/Number of Cycles ]
src
is the address register, the 16 low-order
R2R0
is the address register (A0, A1), the 8
src
src
is the address register,
R2R0
R0
3.2 Functions
src/[src]
src/[src]
DIVU
Page= 212
src
src
src
src
and
and
and
is