M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 117

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
LDC
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
J
[ Flag Change ]
Chapter 3
[ Description Example ]
1 .
*4 Operation is performed on the stack pointer indicated by the U flag.
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM16/#IMM24
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0//A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM16/#IMM24
Change
9
LDC
dest
0 .
Flag
B
• This instruction transfers
• When memory is specified for
*1 The low-order 8 bit of src is transferred.
*2 The low-order 24 bit of src is transferred.
*3 Set even number for SP, ISP and INTB even though odd number can be set. It is more effective to set
LDC
0
0
even number for operation.
3
1
2
9
0
0 -
0
*5 *5 *5 *5 *5 *5 *5 *5
U
2 bytes : DMD0*
4 bytes*
6
1
0 .
0
src
0
5
3 .
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
I
Functions
1
src,dest
A0,FB
2
O
p
: FB, SB, SP*
a
g
e
B
src
99
1
, DMD1*
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
f o
src
3
Z
3
3
5
to the control register indicated by
, ISP*
src
D
1
, FLG, DCT0, DCT1, DRC0, DRC1, SVF
Transfer to control register
, the following bytes of memory are required.
LoaD Control register
3
, INTB*
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
*5 The flag changes only when
3
, VCT, SVP, DMA0, DMA1, DRA0, DRA1, DSA0, DSA1
DMD0
DRC0
FB
INTB
DMA0
DSA0
[ Instruction Code/Number of Cycles ]
DMD1
DRC1
SB
VCT
DMA1
DSA1
dest
.
dest
dest
DCT0
FLG
SP*
SVP
DRA0
is FLG.
4
3.2 Functions
DCT1
SVF
ISP
DRA1
LDC
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