M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 336

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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5.5 Interrupt Priority
5.6 Multiple Interrupts
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Chapter 5
*1 Hardware priority varies with each M32C model. Please refer to your M32C User’s Manual.
Figure 5.5.1. Interrupt priority that is set in hardware
If two or more interrupt requests are sampled active at the same time, whichever interrupt request is ac-
knowledged that has the highest priority.
Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the interrupt
priority level select bit accordingly. If some maskable interrupts are assigned the same priority level, the
interrupt that a request came to most in the first place is accepted at first, and then, the priority between
these interrupts is resolved by the priority that is set in hardware
Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer
interrupt have their priority levels set in hardware. Figure 5.5.1 lists the hardware priority levels of these
interrupts.
Software interrupts are not subjected to interrupt priority. They always cause control to branch to an inter-
rupt routine whenever the relevant instruction is executed.
The following shows the internal bit states when control has branched to an interrupt routine:
By setting the interrupt enable flag (I flag) (= 1) in the interrupt routine, you can reenable interrupts so that an
interrupt request can be acknowledged that has higher priority than the processor interrupt priority level
(IPL). Figure 5.6.1 shows how multiple interrupts are handled.
The interrupt requests that have not been acknowledged for their low interrupt priority level are kept pend-
ing. When the IPL is restored by an REIT and FREIT instruction and interrupt priority is resolved against it,
the pending interrupt request is acknowledged if the following condition is met:
1 .
0
9
0 .
B
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
0
0
3
Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match
1
2
9
0
0 -
0
pending interrupt request
6
Interrupt priority level of
1
0 .
0
0
5
3 .
Interrupt
1
_______
p
a
g
e
318
f o
3
3
5
>
Restored processor interrupt
priority level (IPL)
*1
.
5.5 Interrupt Priority