M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 331

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 5.2.1 Interrupt Priority Levels
Chapter 5
1 .
0
Interrupt priority
5.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
level select bit
9
0 .
B
Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When an
interrupt request is generated, the interrupt priority level of this interrupt is compared with the processor
interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is greater than
the processor interrupt priority level (IPL). This means that you can disable any particular interrupt by
setting its interrupt priority level to 0.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to the processor interrupt priority level (IPL).
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag)
• Interrupt request bit
• Interrupt priority level
The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the processor
interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.
When the processor interrupt priority level (IPL) or the interrupt priority level of some interrupt is
changed, the altered level is reflected in interrupt handling at the following timing:
• If the processor interrupt priority level (IPL) is changed by an REIT or FREIT instruction, the changed
• If the processor interrupt priority level (IPL) is changed by a POPC, LDC, or LDIPL instruction, the
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
0
1
b2
0
0
0
1
1
1
0
0
level takes effect beginning with the REIT or FREIT instruction.
changed level takes effect beginning with the next instruction.
changed level takes effect beginning with the instruction that is executed two clock or two clock peri-
ods after the last clock of the instruction used.
3
1
2
9
0
b1
0
0
1
1
0
0
1
1
0 -
0
6
1
0 .
0
0
0
1
1
0
1
0
1
0
5
b0
3 .
Interrupt
1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt priority level
p
a
g
e
313
f o
3
3
5
= 1
= 1
> Processor interrupt priority level (IPL)
Priority
order
High
Low
Table 5.2.2 IPL and Interrupt Enable Levels
Processor interrupt
priority level (IPL)
IPL
0
0
0
0
1
1
1
1
2
IPL
1
0
1
1
0
0
1
0
1
IPL
0
1
0
1
0
1
1
0
0
Interrupt levels 5 and above are enabled.
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.
Enabled interrupt priority
levels
5.2 Interrupt Control