M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 329

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Chapter 5
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5.1.3 Hardware Interrupts
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(1) Special interrupts
(2) Peripheral I/O interrupts
(3) High-speed interrupts
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There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts.
Special interrupts are nonmaskable interrupts.
• Reset
• NMI interrupt
• Watchdog timer interrupt
• Address-match interrupt
• Single-step interrupt
These interrupts are generated by the on-chip peripheral functions in the MCU system. The types of on-
chip peripheral functions vary with each M32C model, so do the types of interrupt causes. The interrupt
vector table uses the same software interrupt numbers 0–54 and 57 that are used by the INT instruction.
Peripheral I/O interrupts are maskable interrupts. For details about peripheral I/O interrupts, refer to the
M32C User’s Manual.
For peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is cleared to 0 to
choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The previous U flag
before the interrupt occurred is restored when control returns from the interrupt routine.
High-speed interrupts are interrupts in which the response is executed at high-speed. High-speed inter-
rupt can be used as highest priority in peripheral I/O interrupts.
Execute a FREIT instruction to return from the high-speed interrupt routine.
For details about high-speed interrupt, refer to the M32C User’s Manual.
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A reset occurs when the RESET pin is pulled low.
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This interrupt occurs when the NMI pin is pulled low.
This interrupt is caused by the watchdog timer.
This interrupt occurs when the program's execution address matches the content of the address match
register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated
each time an instruction is executed.
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Interrupt
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5.1 Outline of Interrupt