M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 155

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
SHLNC
[ Syntax ]
[ Operation ]
[ Function ]
J
[ Selectable src/dest ]
[ Flag Change ]
[ Description Example ]
Chapter 3
1 .
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM4/#IMM8*
*1 Indirect instruction addressing [dest] can be used in all addressing except R2R0 and R3R1.
*2 The range of values is -32 < #IMM8 < +32( 0).
Change
Conditions
9
SHLNC.size
0 .
Flag
B
• This instruction logically shifts
• The direction of shift is determined by the sign of
• The number of shifts is -32 to +32. You cannot set values less than -32, equal to 0, or greater than +32.
• When
S*
Z*
*3 When dest is the address register (A0, A1), the flag become undefined.
SHLNC.L
SHLNC.L
SHLNC.L
SHLNC.L
0
0
negative, bits are shifted right. Data which are compensated for shift are 0, regardless of the sign of
src
operation. The 24 low-order bits of the operation result are stored in
3
3
3
1
2
9
0
.
: The flag is set when the operation resulted in MSB = 1; otherwise cleared.
: The flag is set when the operation resulted in 0; otherwise cleared.
0 -
0
U
When
When
6
1
0 .
dest
0
0
5
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
3 .
I
Functions
1
2
src
src
is the address register (A0, A1),
#3,R2R0
#-3,R2R0
#10,Ram:8[A1]
#11,[[A0]]
O
p
a
< 0
> 0
g
e
src,dest
B
src
137
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
S
f o
3
Z
3
5
dest
D
SHift Logical Non Carry
0
left or right the number of bits indicated by
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
L
Shift logical
MSB
MSB
dest
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
is zero-extended to be treated as 32-bit data for the
src
; Logically shifted left
; Logically shifted right
; Logically shifted left
; Logically shifted right
dest/[dest]
dest/[dest]
. When
[ Instruction Code/Number of Cycles ]
src
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
is positive, bits are shifted left; when
LSB
LSB
dest
dest*
.
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
1
src
.
0
SHLNC
3.2
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
Page= 288
Functions